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| author | Masahiro Yamada <yamada.m@jp.panasonic.com> | 2015-02-20 17:04:13 +0900 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2015-02-21 08:23:52 -0500 |
| commit | af9308276028924ff7f84770ddbd26bd7046d6c5 (patch) | |
| tree | 55f2467ec5635acc83c97a92df33036f414d9f1f /arch/arm/mach-at91/include/mach/at91_eefc.h | |
| parent | 0e7368c6c4265c138293802b3315629338bc66d0 (diff) | |
| download | u-boot-imx-af9308276028924ff7f84770ddbd26bd7046d6c5.zip u-boot-imx-af9308276028924ff7f84770ddbd26bd7046d6c5.tar.gz u-boot-imx-af9308276028924ff7f84770ddbd26bd7046d6c5.tar.bz2 | |
ARM: at91: move SoC headers to mach-at91/include/mach
Move arch/arm/include/asm/arch-at91/*
-> arch/arm/mach-at91/include/mach/*
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
Diffstat (limited to 'arch/arm/mach-at91/include/mach/at91_eefc.h')
| -rw-r--r-- | arch/arm/mach-at91/include/mach/at91_eefc.h | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91_eefc.h b/arch/arm/mach-at91/include/mach/at91_eefc.h new file mode 100644 index 0000000..7ffbaee --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91_eefc.h @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2010 + * Reinhard Meyer, reinhard.meyer@emk-elektronik.de + * + * Enhanced Embedded Flash Controller + * Based on AT91SAM9XE datasheet + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef AT91_EEFC_H +#define AT91_EEFC_H + +#ifndef __ASSEMBLY__ + +typedef struct at91_eefc { + u32 fmr; /* Flash Mode Register RW */ + u32 fcr; /* Flash Command Register WO */ + u32 fsr; /* Flash Status Register RO */ + u32 frr; /* Flash Result Register RO */ +} at91_eefc_t; + +#endif /* __ASSEMBLY__ */ + +#define AT91_EEFC_FMR_FWS_MASK 0x00000f00 +#define AT91_EEFC_FMR_FRDY_BIT 0x00000001 + +#define AT91_EEFC_FCR_KEY 0x5a000000 +#define AT91_EEFC_FCR_FARG_MASK 0x00ffff00 +#define AT91_EEFC_FCR_FARG_SHIFT 8 +#define AT91_EEFC_FCR_FCMD_GETD 0x0 +#define AT91_EEFC_FCR_FCMD_WP 0x1 +#define AT91_EEFC_FCR_FCMD_WPL 0x2 +#define AT91_EEFC_FCR_FCMD_EWP 0x3 +#define AT91_EEFC_FCR_FCMD_EWPL 0x4 +#define AT91_EEFC_FCR_FCMD_EA 0x5 +#define AT91_EEFC_FCR_FCMD_SLB 0x8 +#define AT91_EEFC_FCR_FCMD_CLB 0x9 +#define AT91_EEFC_FCR_FCMD_GLB 0xA +#define AT91_EEFC_FCR_FCMD_SGPB 0xB +#define AT91_EEFC_FCR_FCMD_CGPB 0xC +#define AT91_EEFC_FCR_FCMD_GGPB 0xD + +#define AT91_EEFC_FSR_FRDY 1 +#define AT91_EEFC_FSR_FCMDE 2 +#define AT91_EEFC_FSR_FLOCKE 4 + +#endif |