diff options
| author | Hans de Goede <hdegoede@redhat.com> | 2015-08-06 12:08:33 +0200 |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2015-08-14 08:37:36 +0200 |
| commit | d8d079966f5d5cf00c33986aa505ab90bcb259b2 (patch) | |
| tree | 77b003a3e4bd7d9ee120ece720f64a37533bf520 /arch/arm/include | |
| parent | 58332f89b63de484024deae402feeafefc9a43e1 (diff) | |
| download | u-boot-imx-d8d079966f5d5cf00c33986aa505ab90bcb259b2.zip u-boot-imx-d8d079966f5d5cf00c33986aa505ab90bcb259b2.tar.gz u-boot-imx-d8d079966f5d5cf00c33986aa505ab90bcb259b2.tar.bz2 | |
sunxi: display: Fix composite video out on sun5i
The tv-encoder on sun5i is slightly different compared to the one on
sun4i/sun7i.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/clock_sun4i.h | 5 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/display.h | 12 |
2 files changed, 16 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h index a7e25f4..b397809 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h @@ -287,6 +287,11 @@ struct sunxi_ccm_reg { #define CCM_LCD_CH0_CTRL_PLL7 (1 << 24) #define CCM_LCD_CH0_CTRL_PLL3_2X (2 << 24) #define CCM_LCD_CH0_CTRL_PLL7_2X (3 << 24) +#ifdef CONFIG_MACH_SUN5I +#define CCM_LCD_CH0_CTRL_TVE_RST (0x1 << 29) +#else +#define CCM_LCD_CH0_CTRL_TVE_RST 0 /* No separate tve-rst on sun4i/7i */ +#endif #define CCM_LCD_CH0_CTRL_RST (0x1 << 30) #define CCM_LCD_CH0_CTRL_GATE (0x1 << 31) diff --git a/arch/arm/include/asm/arch-sunxi/display.h b/arch/arm/include/asm/arch-sunxi/display.h index 2cc3916..b64f310 100644 --- a/arch/arm/include/asm/arch-sunxi/display.h +++ b/arch/arm/include/asm/arch-sunxi/display.h @@ -196,7 +196,9 @@ struct sunxi_lcdc_reg { u8 res3[0x44]; /* 0xac */ u32 tcon1_io_polarity; /* 0xf0 */ u32 tcon1_io_tristate; /* 0xf4 */ - u8 res4[0x128]; /* 0xf8 */ + u8 res4[0x108]; /* 0xf8 */ + u32 mux_ctrl; /* 0x200 */ + u8 res5[0x1c]; /* 0x204 */ u32 lvds_ana0; /* 0x220 */ u32 lvds_ana1; /* 0x224 */ }; @@ -385,6 +387,10 @@ struct sunxi_tve_reg { #define SUNXI_LCDC_TCON1_TIMING_H_TOTAL(n) (((n) - 1) << 16) #define SUNXI_LCDC_TCON1_TIMING_V_BP(n) (((n) - 1) << 0) #define SUNXI_LCDC_TCON1_TIMING_V_TOTAL(n) ((n) << 16) +#define SUNXI_LCDC_MUX_CTRL_SRC0_MASK (0xf << 0) +#define SUNXI_LCDC_MUX_CTRL_SRC0(x) ((x) << 0) +#define SUNXI_LCDC_MUX_CTRL_SRC1_MASK (0xf << 4) +#define SUNXI_LCDC_MUX_CTRL_SRC1(x) ((x) << 4) #ifdef CONFIG_SUNXI_GEN_SUN6I #define SUNXI_LCDC_LVDS_ANA0 0x40040320 #define SUNXI_LCDC_LVDS_ANA0_EN_MB (1 << 31) @@ -506,7 +512,11 @@ struct sunxi_tve_reg { #define SUNXI_TVE_CFG0_PAL 0x07030001 #define SUNXI_TVE_CFG0_NTSC 0x07030000 #define SUNXI_TVE_DAC_CFG0_VGA 0x403e1ac7 +#ifdef CONFIG_MACH_SUN5I +#define SUNXI_TVE_DAC_CFG0_COMPOSITE 0x433f0009 +#else #define SUNXI_TVE_DAC_CFG0_COMPOSITE 0x403f0008 +#endif #define SUNXI_TVE_FILTER_COMPOSITE 0x00000120 #define SUNXI_TVE_CHROMA_FREQ_PAL_M 0x21e6efe3 #define SUNXI_TVE_CHROMA_FREQ_PAL_NC 0x21f69446 |