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| author | Tang Yuantian <Yuantian.Tang@nxp.com> | 2016-08-08 15:07:20 +0800 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-10-06 09:52:59 -0700 |
| commit | 4de6ce1594fcff6fa9e626d094fa922f4889e167 (patch) | |
| tree | 365d7229e766c3dd6fc9ad21627586662bc5b4fe /arch/arm/include | |
| parent | f0beb49290c4e6af7d88895a15a45bbea38318fe (diff) | |
| download | u-boot-imx-4de6ce1594fcff6fa9e626d094fa922f4889e167.zip u-boot-imx-4de6ce1594fcff6fa9e626d094fa922f4889e167.tar.gz u-boot-imx-4de6ce1594fcff6fa9e626d094fa922f4889e167.tar.bz2 | |
armv8: fsl-lsch2: enable snoopable sata read and write
By default the SATA IP on the ls1043a/ls1046a SoCs does not
generating coherent/snoopable transactions. This patch enable
it in the SCFG_SNPCNFGCR register along with sata axicc register.
In addition, the dma-coherent property must be set on the SATA
controller nodes.
Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
[York Sun: Reformatted commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 2 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/soc.h | 1 |
2 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index df51871..3d00909 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -335,6 +335,8 @@ struct ccsr_gur { #define SCFG_SNPCNFGCR_SECRDSNP 0x80000000 #define SCFG_SNPCNFGCR_SECWRSNP 0x40000000 +#define SCFG_SNPCNFGCR_SATARDSNP 0x00800000 +#define SCFG_SNPCNFGCR_SATAWRSNP 0x00400000 /* Supplemental Configuration Unit */ struct ccsr_scfg { diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 0729b7f..58e90d8 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -61,6 +61,7 @@ struct cpu_type { /* ahci port register default value */ #define AHCI_PORT_PHY_1_CFG 0xa003fffe #define AHCI_PORT_TRANS_CFG 0x08000029 +#define AHCI_PORT_AXICC_CFG 0x3fffffff /* AHCI (sata) register map */ struct ccsr_ahci { |