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| author | Bhupesh Sharma <bhupesh.sharma@freescale.com> | 2015-03-19 09:20:43 -0700 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-04-21 10:26:29 -0700 |
| commit | 422cb08acb1bc9a05ffa68ba68b4e196dad1af5b (patch) | |
| tree | 1aae2fc085d1317f5ee6b9e26f44fffa5435be36 /arch/arm/include | |
| parent | 1fb5ff9ae732d63c8810bd1a6922273e14329093 (diff) | |
| download | u-boot-imx-422cb08acb1bc9a05ffa68ba68b4e196dad1af5b.zip u-boot-imx-422cb08acb1bc9a05ffa68ba68b4e196dad1af5b.tar.gz u-boot-imx-422cb08acb1bc9a05ffa68ba68b4e196dad1af5b.tar.bz2 | |
armv8/fsl-lsch3: Add Freescale Debug Server driver
The Debug Server driver is responsible for loading the Debug
server FW on the Service Processor (Cortex-A5 core) on LS2085A like
SoCs and then polling for the successful initialization of the same.
TOP MEM HIDE is adjusted to ensure the space required by Debug Server
FW is accounted for. MC uses the DDR area which is calculated as:
MC DDR region start = Top of DDR - area reserved by Debug Server FW
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-lsch3/config.h | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index b140c1f..59d10bf 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -30,6 +30,15 @@ #define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \ 0x18A0) +/* SP (Cortex-A5) related */ +#define CONFIG_SYS_FSL_SP_ADDR (CONFIG_SYS_IMMR + 0x00F00000) +#define CONFIG_SYS_FSL_SP_VSG_GIC_ADDR (CONFIG_SYS_FSL_SP_ADDR) +#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR1 (CONFIG_SYS_FSL_SP_ADDR) +#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2 \ + (CONFIG_SYS_FSL_SP_ADDR + 0x0008) +#define CONFIG_SYS_FSL_SP_LOOPBACK_DUART \ + (CONFIG_SYS_FSL_SP_ADDR + 0x1000) + #define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL #define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL #define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL @@ -88,7 +97,6 @@ #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 - /* IFC */ #define CONFIG_SYS_FSL_IFC_LE |