Merge branch 'master' of http://git.denx.de/u-boot-sunxi

4 files changed, 79 insertions, 50 deletions

diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index dae6069..f403742 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -94,6 +94,13 @@
 #define SUNXI_TWI0_BASE			0x01c2ac00
 #define SUNXI_TWI1_BASE			0x01c2b000
 #define SUNXI_TWI2_BASE			0x01c2b400
+#ifdef CONFIG_MACH_SUN6I
+#define SUNXI_TWI3_BASE			0x01c0b800
+#endif
+#ifdef CONFIG_MACH_SUN7I
+#define SUNXI_TWI3_BASE			0x01c2b800
+#define SUNXI_TWI4_BASE			0x01c2c000
+#endif
 
 #define SUNXI_CAN_BASE			0x01c2bc00
 
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index f2c247d..ae7cbb7 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -84,7 +84,7 @@ struct sunxi_gpio_reg {
 #define GPIO_CFG_INDEX(pin)	(((pin) & 0x1f) >> 3)
 #define GPIO_CFG_OFFSET(pin)	((((pin) & 0x1f) & 0x7) << 2)
 
-#define GPIO_DRV_INDEX(pin)   (((pin) & 0x1f) >> 4)
+#define GPIO_DRV_INDEX(pin)	(((pin) & 0x1f) >> 4)
 #define GPIO_DRV_OFFSET(pin)	((((pin) & 0x1f) & 0xf) << 1)
 
 #define GPIO_PULL_INDEX(pin)	(((pin) & 0x1f) >> 4)
@@ -142,71 +142,77 @@ enum sunxi_gpio_number {
 #define SUNXI_GPIO_INPUT	0
 #define SUNXI_GPIO_OUTPUT	1
 
-#define SUNXI_GPA0_EMAC		2
-#define SUN6I_GPA0_GMAC		2
-#define SUN7I_GPA0_GMAC		5
-
-#define SUNXI_GPB0_TWI0		2
-
-#define SUN4I_GPB22_UART0_TX	2
-#define SUN4I_GPB23_UART0_RX	2
-
-#define SUN5I_GPB19_UART0_TX	2
-#define SUN5I_GPB20_UART0_RX	2
-
-#define SUNXI_GPC6_SDC2		3
-
-#define SUNXI_GPD0_LCD0		2
-#define SUNXI_GPD0_LVDS0	3
-
-#define SUNXI_GPF0_SDC0		2
-
-#define SUNXI_GPF2_SDC0		2
-
-#ifdef CONFIG_MACH_SUN8I
-#define SUNXI_GPF2_UART0_TX	3
-#define SUNXI_GPF4_UART0_RX	3
-#else
-#define SUNXI_GPF2_UART0_TX	4
-#define SUNXI_GPF4_UART0_RX	4
-#endif
-
-#define SUN4I_GPG0_SDC1		4
-
-#define SUN5I_GPG3_SDC1		2
-
-#define SUN5I_GPG3_UART1_TX	4
-#define SUN5I_GPG4_UART1_RX	4
-
-#define SUN4I_GPH22_SDC1	5
-
-#define SUN6I_GPH20_UART0_TX	2
-#define SUN6I_GPH21_UART0_RX	2
-
-#define SUN4I_GPI4_SDC3		2
+#define SUNXI_GPA_EMAC		2
+#define SUN6I_GPA_GMAC		2
+#define SUN7I_GPA_GMAC		5
+#define SUN6I_GPA_SDC2		5
+#define SUN6I_GPA_SDC3		4
+
+#define SUN4I_GPB_TWI0		2
+#define SUN4I_GPB_TWI1		2
+#define SUN5I_GPB_TWI1		2
+#define SUN4I_GPB_TWI2		2
+#define SUN5I_GPB_TWI2		2
+#define SUN4I_GPB_UART0		2
+#define SUN5I_GPB_UART0		2
+
+#define SUNXI_GPC_SDC2		3
+#define SUN6I_GPC_SDC3		4
+
+#define SUN8I_GPD_SDC1		3
+#define SUNXI_GPD_LCD0		2
+#define SUNXI_GPD_LVDS0		3
+
+#define SUN5I_GPE_SDC2		3
+#define SUN8I_GPE_TWI2		3
+
+#define SUNXI_GPF_SDC0		2
+#define SUNXI_GPF_UART0		4
+#define SUN8I_GPF_UART0		3
+
+#define SUN4I_GPG_SDC1		4
+#define SUN5I_GPG_SDC1		2
+#define SUN6I_GPG_SDC1		2
+#define SUN8I_GPG_SDC1		2
+#define SUN6I_GPG_TWI3		2
+#define SUN5I_GPG_UART1		4
+
+#define SUN4I_GPH_SDC1		5
+#define SUN6I_GPH_TWI0		2
+#define SUN8I_GPH_TWI0		2
+#define SUN6I_GPH_TWI1		2
+#define SUN8I_GPH_TWI1		2
+#define SUN6I_GPH_TWI2		2
+#define SUN6I_GPH_UART0		2
+
+#define SUNXI_GPI_SDC3		2
+#define SUN7I_GPI_TWI3		3
+#define SUN7I_GPI_TWI4		3
 
 #define SUN6I_GPL0_R_P2WI_SCK	3
 #define SUN6I_GPL1_R_P2WI_SDA	3
 
-#define SUN8I_GPL0_R_RSB_SCK	2
-#define SUN8I_GPL1_R_RSB_SDA	2
-#define SUN8I_GPL2_R_UART_TX	2
-#define SUN8I_GPL3_R_UART_RX	2
+#define SUN8I_GPL_R_RSB		2
+#define SUN8I_GPL_R_UART	2
 
-#define SUN9I_GPN0_R_RSB_SCK	3
-#define SUN9I_GPN1_R_RSB_SDA    3
+#define SUN9I_GPN_R_RSB		3
 
 /* GPIO pin pull-up/down config */
 #define SUNXI_GPIO_PULL_DISABLE	0
 #define SUNXI_GPIO_PULL_UP	1
 #define SUNXI_GPIO_PULL_DOWN	2
 
+/* Virtual AXP0 GPIOs */
+#define SUNXI_GPIO_AXP0_VBUS_DETECT	8
+#define SUNXI_GPIO_AXP0_VBUS_ENABLE	9
+
 void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val);
 void sunxi_gpio_set_cfgpin(u32 pin, u32 val);
 int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset);
 int sunxi_gpio_get_cfgpin(u32 pin);
 int sunxi_gpio_set_drv(u32 pin, u32 val);
 int sunxi_gpio_set_pull(u32 pin, u32 val);
+int sunxi_name_to_gpio_bank(const char *name);
 int sunxi_name_to_gpio(const char *name);
 #define name_to_gpio(name) sunxi_name_to_gpio(name)
 
diff --git a/arch/arm/include/asm/arch-sunxi/i2c.h b/arch/arm/include/asm/arch-sunxi/i2c.h
index dc5406b..561cd2b 100644
--- a/arch/arm/include/asm/arch-sunxi/i2c.h
+++ b/arch/arm/include/asm/arch-sunxi/i2c.h
@@ -8,7 +8,22 @@
 
 #include <asm/arch/cpu.h>
 
-#define CONFIG_I2C_MVTWSI_BASE	SUNXI_TWI0_BASE
+#ifdef CONFIG_I2C0_ENABLE
+#define CONFIG_I2C_MVTWSI_BASE0	SUNXI_TWI0_BASE
+#endif
+#ifdef CONFIG_I2C1_ENABLE
+#define CONFIG_I2C_MVTWSI_BASE1	SUNXI_TWI1_BASE
+#endif
+#ifdef CONFIG_I2C2_ENABLE
+#define CONFIG_I2C_MVTWSI_BASE2	SUNXI_TWI2_BASE
+#endif
+#ifdef CONFIG_I2C3_ENABLE
+#define CONFIG_I2C_MVTWSI_BASE3	SUNXI_TWI3_BASE
+#endif
+#ifdef CONFIG_I2C4_ENABLE
+#define CONFIG_I2C_MVTWSI_BASE4	SUNXI_TWI4_BASE
+#endif
+
 /* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */
 #define CONFIG_SYS_TCLK		24000000
 
diff --git a/arch/arm/include/asm/arch-sunxi/usbc.h b/arch/arm/include/asm/arch-sunxi/usbc.h
index 1330733..ab0f272 100644
--- a/arch/arm/include/asm/arch-sunxi/usbc.h
+++ b/arch/arm/include/asm/arch-sunxi/usbc.h
@@ -20,4 +20,5 @@ void sunxi_usbc_enable(int index);
 void sunxi_usbc_disable(int index);
 void sunxi_usbc_vbus_enable(int index);
 void sunxi_usbc_vbus_disable(int index);
+int sunxi_usbc_vbus_detect(int index);
 void sunxi_usbc_enable_squelch_detect(int index, int enable);