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| author | Hou Zhiqiang <Zhiqiang.Hou@nxp.com> | 2016-09-29 12:42:44 +0800 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-10-06 09:57:36 -0700 |
| commit | 0ea3671d35dc5a6f2555bb5307d76e229e81f47d (patch) | |
| tree | 1cbe9bcac69186e6b995f66b8e976d85cbb6ed64 /arch/arm/include | |
| parent | adee1d4c9eb16a49ec1396b3367d027b7c3d2940 (diff) | |
| download | u-boot-imx-0ea3671d35dc5a6f2555bb5307d76e229e81f47d.zip u-boot-imx-0ea3671d35dc5a6f2555bb5307d76e229e81f47d.tar.gz u-boot-imx-0ea3671d35dc5a6f2555bb5307d76e229e81f47d.tar.bz2 | |
armv8/fsl-lsch2: Implement workaround for PIN MUX erratum A010539
Pin mux logic has 2 options in priority order, one is through RCW_SRC
and then through RCW_Fields. In case of QSPI booting, RCW_SRC logic
takes the priority for SPI pads and do not allow RCW_BASE and SPI_EXT
to control the SPI muxing. But actually those are DSPI controller's
pads instead of QSPI controller's, so this workaround allows RCW
fields SPI_BASE and SPI_EXT to control relevant pads muxing.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[York Sun: Reformatted commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 3d00909..d88543d 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -168,6 +168,8 @@ struct sys_info { (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) /* Device Configuration and Pin Control */ +#define DCFG_DCSR_PORCR1 0x0 + struct ccsr_gur { u32 porsr1; /* POR status 1 */ #define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000 |