summaryrefslogtreecommitdiff
path: root/arch/arm/include
diff options
context:
space:
mode:
authorR Sricharan <r.sricharan@ti.com>2013-03-04 20:04:44 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2013-03-28 09:06:49 +0100
commit96fdbec2f96c9e11758c8742409069eeef841722 (patch)
treef58248e8a686f7a44dc39396a61072292fd1902c /arch/arm/include
parentdfa41387155daed35cc6b294b2390641aa887a1d (diff)
downloadu-boot-imx-96fdbec2f96c9e11758c8742409069eeef841722.zip
u-boot-imx-96fdbec2f96c9e11758c8742409069eeef841722.tar.gz
u-boot-imx-96fdbec2f96c9e11758c8742409069eeef841722.tar.bz2
ARM: mmu: Introduce weak dram_bank_setup function
Introduce a weak version of dram_bank_setup function to allow a platform specific function. This is used in the subsequent patch to setup dram region without 'XN' attribute in order to enable the region under client permissions. Signed-off-by: R Sricharan <r.sricharan@ti.com> Cc: Vincent Stehle <v-stehle@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Diffstat (limited to 'arch/arm/include')
-rw-r--r--arch/arm/include/asm/cache.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
index 416d2c8..8153484 100644
--- a/arch/arm/include/asm/cache.h
+++ b/arch/arm/include/asm/cache.h
@@ -43,6 +43,7 @@ void l2_cache_enable(void);
void l2_cache_disable(void);
void set_section_dcache(int section, enum dcache_option option);
+void dram_bank_mmu_setup(int bank);
/*
* The current upper bound for ARM L1 data cache line sizes is 64 bytes. We
* use that value for aligning DMA buffers unless the board config has specified