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authorAlbert ARIBAUD <albert.u.boot@aribaud.net>2013-04-04 15:44:57 +0200
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2013-04-04 15:44:57 +0200
commitfed029f3c31b7d5df674b5090a13356b631918c7 (patch)
treef1948b23396505a4f5568ab9d37800235b815e0b /arch/arm/include/asm
parentbe08abc2429c2e9cbce3d0abc1d315171d683520 (diff)
parent4fdebefa453a58c7b4ca653ab40f7a9791aba6c9 (diff)
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Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'
Diffstat (limited to 'arch/arm/include/asm')
-rw-r--r--arch/arm/include/asm/arch-exynos/clk.h15
-rw-r--r--arch/arm/include/asm/arch-exynos/cpu.h10
-rw-r--r--arch/arm/include/asm/arch-exynos/dp_info.h1
-rw-r--r--arch/arm/include/asm/arch-exynos/periph.h5
4 files changed, 27 insertions, 4 deletions
diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h
index 1935b0b..73f8063 100644
--- a/arch/arm/include/asm/arch-exynos/clk.h
+++ b/arch/arm/include/asm/arch-exynos/clk.h
@@ -29,6 +29,12 @@
#define VPLL 4
#define BPLL 5
+enum pll_src_bit {
+ EXYNOS_SRC_MPLL = 6,
+ EXYNOS_SRC_EPLL,
+ EXYNOS_SRC_VPLL,
+};
+
unsigned long get_pll_clk(int pllreg);
unsigned long get_arm_clk(void);
unsigned long get_i2c_clk(void);
@@ -44,4 +50,13 @@ int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq);
int set_epll_clk(unsigned long rate);
int set_spi_clk(int periph_id, unsigned int rate);
+/**
+ * get the clk frequency of the required peripheral
+ *
+ * @param peripheral Peripheral id
+ *
+ * @return frequency of the peripheral clk
+ */
+unsigned long clock_get_periph_rate(int peripheral);
+
#endif
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
index eb34422..f76e489 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -62,6 +62,7 @@
#define EXYNOS4_GPIO_PART4_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4_DP_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4_SPI_ISP_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4_ACE_SFR_BASE DEVICE_NOT_AVAILABLE
/* EXYNOS4X12 */
#define EXYNOS4X12_GPIO_PART3_BASE 0x03860000
@@ -92,9 +93,10 @@
#define EXYNOS4X12_ADC_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_DP_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_MODEM_BASE DEVICE_NOT_AVAILABLE
-#define EXYNOS4X12_I2S_BASE DEVICE_NOT_AVAILABLE
-#define EXYNOS4X12_SPI_BASE DEVICE_NOT_AVAILABLE
-#define EXYNOS4X12_SPI_ISP_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_I2S_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_SPI_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_SPI_ISP_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_ACE_SFR_BASE DEVICE_NOT_AVAILABLE
/* EXYNOS5 Common*/
#define EXYNOS5_I2C_SPACING 0x10000
@@ -106,6 +108,7 @@
#define EXYNOS5_SWRESET 0x10040400
#define EXYNOS5_SYSREG_BASE 0x10050000
#define EXYNOS5_WATCHDOG_BASE 0x101D0000
+#define EXYNOS5_ACE_SFR_BASE 0x10830000
#define EXYNOS5_DMC_PHY0_BASE 0x10C00000
#define EXYNOS5_DMC_PHY1_BASE 0x10C10000
#define EXYNOS5_GPIO_PART3_BASE 0x10D10000
@@ -205,6 +208,7 @@ static inline unsigned int samsung_get_base_##device(void) \
SAMSUNG_BASE(adc, ADC_BASE)
SAMSUNG_BASE(clock, CLOCK_BASE)
+SAMSUNG_BASE(ace_sfr, ACE_SFR_BASE)
SAMSUNG_BASE(dp, DP_BASE)
SAMSUNG_BASE(sysreg, SYSREG_BASE)
SAMSUNG_BASE(fimd, FIMD_BASE)
diff --git a/arch/arm/include/asm/arch-exynos/dp_info.h b/arch/arm/include/asm/arch-exynos/dp_info.h
index 102b709..ff16361 100644
--- a/arch/arm/include/asm/arch-exynos/dp_info.h
+++ b/arch/arm/include/asm/arch-exynos/dp_info.h
@@ -199,7 +199,6 @@ enum {
struct exynos_dp_platform_data {
struct edp_device_info *edp_dev_info;
- void (*phy_enable)(unsigned int);
};
#ifdef CONFIG_EXYNOS_DP
diff --git a/arch/arm/include/asm/arch-exynos/periph.h b/arch/arm/include/asm/arch-exynos/periph.h
index 89bcdfc..e5aed4b 100644
--- a/arch/arm/include/asm/arch-exynos/periph.h
+++ b/arch/arm/include/asm/arch-exynos/periph.h
@@ -61,6 +61,11 @@ enum periph_id {
PERIPH_ID_SPI3,
PERIPH_ID_SPI4,
PERIPH_ID_SDMMC4,
+ PERIPH_ID_PWM0,
+ PERIPH_ID_PWM1,
+ PERIPH_ID_PWM2,
+ PERIPH_ID_PWM3,
+ PERIPH_ID_PWM4,
PERIPH_ID_COUNT,
PERIPH_ID_NONE = -1,