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| author | York Sun <york.sun@nxp.com> | 2016-09-13 12:40:30 -0700 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-10-06 09:56:57 -0700 |
| commit | ef9a5fd8643ebdd5f492a5b09725134999f428b9 (patch) | |
| tree | aae37bebfc242c7f0f63e8e2fa3b735440deb056 /arch/arm/include/asm | |
| parent | 5d1a7a9d209fd9b8ffca1f3f27139f372a225e16 (diff) | |
| download | u-boot-imx-ef9a5fd8643ebdd5f492a5b09725134999f428b9.zip u-boot-imx-ef9a5fd8643ebdd5f492a5b09725134999f428b9.tar.gz u-boot-imx-ef9a5fd8643ebdd5f492a5b09725134999f428b9.tar.bz2 | |
armv8: fsl-layerscape: Fix "cpu status" command
The core position is not continuous for some SoCs. For example,
valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some
registers (including boot release register) only count existing
cores. Current implementation of cpu_mask() complies with the
continuous numbering. However, command "cpu status" queries the
spin table with actual core position. Add functions to calculate
core position from core number, to correctly calculate offsets.
Tested on LS2080ARDB and LS1043ARDB.
Signed-off-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/include/asm')
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/mp.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/mp.h b/arch/arm/include/asm/arch-fsl-layerscape/mp.h index e46e076..f7306ff 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/mp.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/mp.h @@ -34,5 +34,6 @@ void *get_spin_tbl_addr(void); phys_addr_t determine_mp_bootpg(void); void secondary_boot_func(void); int is_core_online(u64 cpu_id); +u32 cpu_pos_mask(void); #endif #endif /* _FSL_LAYERSCAPE_MP_H */ |