Merge branch 'master' of git://git.denx.de/u-boot-arm

13 files changed, 837 insertions, 28 deletions

diff --git a/arch/arm/include/asm/arch-uniphier/arm-mpcore.h b/arch/arm/include/asm/arch-uniphier/arm-mpcore.h
new file mode 100644
index 0000000..cf7cd46
--- /dev/null
+++ b/arch/arm/include/asm/arch-uniphier/arm-mpcore.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef ARCH_ARM_MPCORE_H
+#define ARCH_ARM_MPCORE_H
+
+/* Snoop Control Unit */
+#define SCU_OFFSET		0x00
+
+/* SCU Control Register */
+#define SCU_CTRL		0x00
+/* SCU Configuration Register */
+#define SCU_CONF		0x04
+/* SCU CPU Power Status Register */
+#define SCU_PWR_STATUS		0x08
+/* SCU Invalidate All Registers in Secure State */
+#define SCU_INV_ALL		0x0C
+/* SCU Filtering Start Address Register */
+#define SCU_FILTER_START	0x40
+/* SCU Filtering End Address Register */
+#define SCU_FILTER_END		0x44
+/* SCU Access Control Register */
+#define SCU_SAC			0x50
+/* SCU Non-secure Access Control Register */
+#define SCU_SNSAC		0x54
+
+/* Global Timer */
+#define GLOBAL_TIMER_OFFSET	0x200
+
+/* Global Timer Counter Registers */
+#define GTIMER_CNT_L		0x00
+#define GTIMER_CNT_H		0x04
+/* Global Timer Control Register */
+#define GTIMER_CTRL		0x08
+/* Global Timer Interrupt Status Register */
+#define GTIMER_STAT		0x0C
+/* Comparator Value Registers */
+#define GTIMER_CMP_L		0x10
+#define GTIMER_CMP_H		0x14
+/* Auto-increment Register */
+#define GTIMER_INC		0x18
+
+#endif /* ARCH_ARM_MPCORE_H */
diff --git a/arch/arm/include/asm/arch-uniphier/bcu-regs.h b/arch/arm/include/asm/arch-uniphier/bcu-regs.h
new file mode 100644
index 0000000..0dfd94e
--- /dev/null
+++ b/arch/arm/include/asm/arch-uniphier/bcu-regs.h
@@ -0,0 +1,30 @@
+/*
+ * UniPhier BCU (Bus Control Unit) registers
+ *
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef ARCH_BCU_REGS_H
+#define ARCH_BCU_REGS_H
+
+#define	BCU_BASE		0x50080000
+
+#define	BCSCR(x)                (BCU_BASE + 0x180 + (x) * 4)
+#define	BCSCR0			(BCSCR(0))
+#define	BCSCR1			(BCSCR(1))
+#define	BCSCR2			(BCSCR(2))
+#define	BCSCR3			(BCSCR(3))
+#define	BCSCR4			(BCSCR(4))
+#define	BCSCR5			(BCSCR(5))
+
+#define	BCIPPCCHR(x)		(BCU_BASE + 0x0280 + (x) * 4)
+#define	BCIPPCCHR0		(BCIPPCCHR(0))
+#define	BCIPPCCHR1		(BCIPPCCHR(1))
+#define	BCIPPCCHR2		(BCIPPCCHR(2))
+#define	BCIPPCCHR3		(BCIPPCCHR(3))
+#define	BCIPPCCHR4		(BCIPPCCHR(4))
+#define	BCIPPCCHR5		(BCIPPCCHR(5))
+
+#endif  /* ARCH_BCU_REGS_H */
diff --git a/arch/arm/include/asm/arch-uniphier/board.h b/arch/arm/include/asm/arch-uniphier/board.h
new file mode 100644
index 0000000..e6ba4e4
--- /dev/null
+++ b/arch/arm/include/asm/arch-uniphier/board.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef ARCH_BOARD_H
+#define ARCH_BOARD_H
+
+#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) || \
+	defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
+void support_card_reset(void);
+void support_card_init(void);
+int check_support_card(void);
+#else
+#define support_card_reset() do {} while (0)
+#define support_card_init()  do {} while (0)
+static inline int check_support_card(void)
+{
+	return 0;
+}
+#endif
+
+static inline void uniphier_board_reset(void)
+{
+	support_card_reset();
+}
+
+static inline void uniphier_board_init(void)
+{
+	support_card_init();
+}
+
+#endif /* ARCH_BOARD_H */
diff --git a/arch/arm/include/asm/arch-uniphier/boot-device.h b/arch/arm/include/asm/arch-uniphier/boot-device.h
new file mode 100644
index 0000000..6987f57
--- /dev/null
+++ b/arch/arm/include/asm/arch-uniphier/boot-device.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_BOOT_DEVICE_H_
+#define _ASM_BOOT_DEVICE_H_
+
+u32 get_boot_mode_sel(void);
+
+struct boot_device_info {
+	u32 type;
+	char *info;
+};
+
+extern struct boot_device_info boot_device_table[];
+
+#endif /* _ASM_BOOT_DEVICE_H_ */
diff --git a/arch/arm/include/asm/arch-uniphier/led.h b/arch/arm/include/asm/arch-uniphier/led.h
new file mode 100644
index 0000000..21277da
--- /dev/null
+++ b/arch/arm/include/asm/arch-uniphier/led.h
@@ -0,0 +1,101 @@
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef ARCH_LED_H
+#define ARCH_LED_H
+
+#include <config.h>
+
+#define LED_CHAR_0	0x7e
+#define LED_CHAR_1	0x0c
+#define LED_CHAR_2	0xb6
+#define LED_CHAR_3	0x9e
+#define LED_CHAR_4	0xcc
+#define LED_CHAR_5	0xda
+#define LED_CHAR_6	0xfa
+#define LED_CHAR_7	0x4e
+#define LED_CHAR_8	0xfe
+#define LED_CHAR_9	0xde
+
+#define LED_CHAR_A	0xee
+#define LED_CHAR_B	0xf8
+#define LED_CHAR_C	0x72
+#define LED_CHAR_D	0xbc
+#define LED_CHAR_E	0xf2
+#define LED_CHAR_F	0xe2
+#define LED_CHAR_G	0x7a
+#define LED_CHAR_H	0xe8
+#define LED_CHAR_I	0x08
+#define LED_CHAR_J	0x3c
+#define LED_CHAR_K	0xea
+#define LED_CHAR_L	0x70
+#define LED_CHAR_M	0x6e
+#define LED_CHAR_N	0xa8
+#define LED_CHAR_O	0xb8
+#define LED_CHAR_P	0xe6
+#define LED_CHAR_Q	0xce
+#define LED_CHAR_R	0xa0
+#define LED_CHAR_S	0xc8
+#define LED_CHAR_T	0x8c
+#define LED_CHAR_U	0x7c
+#define LED_CHAR_V	0x54
+#define LED_CHAR_W	0xfc
+#define LED_CHAR_X	0xec
+#define LED_CHAR_Y	0xdc
+#define LED_CHAR_Z	0xa4
+
+#define LED_CHAR_SPACE	0x00
+#define LED_CHAR_DOT	0x01
+
+#define LED_CHAR_	(LED_CHAR_SPACE)
+
+/** Macro to translate 4 characters into integer to display led */
+#define LED_C2I(C0, C1, C2, C3)			\
+	(~(					\
+		(LED_CHAR_##C0 << 24) |		\
+		(LED_CHAR_##C1 << 16) |		\
+		(LED_CHAR_##C2 <<  8) |		\
+		(LED_CHAR_##C3)			\
+	))
+
+#if defined(CONFIG_SUPPORT_CARD_LED_BASE)
+
+#define LED_ADDR    CONFIG_SUPPORT_CARD_LED_BASE
+
+#ifdef __ASSEMBLY__
+
+#define led_write(C0, C1, C2, C3)  raw_led_write LED_C2I(C0, C1, C2, C3)
+.macro raw_led_write data
+	ldr r0, =\data
+	ldr r1, =LED_ADDR
+	str r0, [r1]
+.endm
+
+#else /* __ASSEMBLY__ */
+
+#include <asm/io.h>
+
+#define led_write(C0, C1, C2, C3)		\
+do {						\
+	raw_led_write(LED_C2I(C0, C1, C2, C3));	\
+} while (0)
+
+static inline void raw_led_write(u32 data)
+{
+	writel(data, LED_ADDR);
+}
+
+#endif /* __ASSEMBLY__ */
+
+#else /* CONFIG_SUPPORT_CARD_LED_BASE */
+
+#define led_write(C0, C1, C2, C3)
+#define raw_led_write(x)
+
+#endif /* CONFIG_SUPPORT_CARD_LED_BASE */
+
+#endif /* ARCH_LED_H */
diff --git a/arch/arm/include/asm/arch-uniphier/sbc-regs.h b/arch/arm/include/asm/arch-uniphier/sbc-regs.h
new file mode 100644
index 0000000..8e41078
--- /dev/null
+++ b/arch/arm/include/asm/arch-uniphier/sbc-regs.h
@@ -0,0 +1,108 @@
+/*
+ * UniPhier SBC (System Bus Controller) registers
+ *
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef ARCH_SBC_REGS_H
+#define ARCH_SBC_REGS_H
+
+#define	SBBASE_BASE		0x58c00100
+#define	SBBASE(x)		(SBBASE_BASE + (x) * 0x10)
+
+#define	SBBASE0			(SBBASE(0))
+#define	SBBASE1			(SBBASE(1))
+#define	SBBASE2			(SBBASE(2))
+#define	SBBASE3			(SBBASE(3))
+#define	SBBASE4			(SBBASE(4))
+#define	SBBASE5			(SBBASE(5))
+#define	SBBASE6			(SBBASE(6))
+#define	SBBASE7			(SBBASE(7))
+
+#define	SBBASE_BANK_ENABLE	(0x00000001)
+
+#define	SBCTRL_BASE		0x58c00200
+#define	SBCTRL(x, y)		(SBCTRL_BASE + (x) * 0x10 + (y) * 4)
+
+#define	SBCTRL00		SBCTRL(0, 0)
+#define	SBCTRL01		SBCTRL(0, 1)
+#define	SBCTRL02		SBCTRL(0, 2)
+#define	SBCTRL03		SBCTRL(0, 3)
+#define	SBCTRL04		(SBCTRL_BASE + 0x100)
+
+#define	SBCTRL10		SBCTRL(1, 0)
+#define	SBCTRL11		SBCTRL(1, 1)
+#define	SBCTRL12		SBCTRL(1, 2)
+#define	SBCTRL13		SBCTRL(1, 3)
+#define	SBCTRL14		(SBCTRL_BASE + 0x110)
+
+#define	SBCTRL20		SBCTRL(2, 0)
+#define	SBCTRL21		SBCTRL(2, 1)
+#define	SBCTRL22		SBCTRL(2, 2)
+#define	SBCTRL23		SBCTRL(2, 3)
+#define	SBCTRL24		(SBCTRL_BASE + 0x120)
+
+#define	SBCTRL30		SBCTRL(3, 0)
+#define	SBCTRL31		SBCTRL(3, 1)
+#define	SBCTRL32		SBCTRL(3, 2)
+#define	SBCTRL33		SBCTRL(3, 3)
+#define	SBCTRL34		(SBCTRL_BASE + 0x130)
+
+#define	SBCTRL40		SBCTRL(4, 0)
+#define	SBCTRL41		SBCTRL(4, 1)
+#define	SBCTRL42		SBCTRL(4, 2)
+#define	SBCTRL43		SBCTRL(4, 3)
+#define	SBCTRL44		(SBCTRL_BASE + 0x140)
+
+#define	SBCTRL50		SBCTRL(5, 0)
+#define	SBCTRL51		SBCTRL(5, 1)
+#define	SBCTRL52		SBCTRL(5, 2)
+#define	SBCTRL53		SBCTRL(5, 3)
+#define	SBCTRL54		(SBCTRL_BASE + 0x150)
+
+#define	SBCTRL60		SBCTRL(6, 0)
+#define	SBCTRL61		SBCTRL(6, 1)
+#define	SBCTRL62		SBCTRL(6, 2)
+#define	SBCTRL63		SBCTRL(6, 3)
+#define	SBCTRL64		(SBCTRL_BASE + 0x160)
+
+#define	SBCTRL70		SBCTRL(7, 0)
+#define	SBCTRL71		SBCTRL(7, 1)
+#define	SBCTRL72		SBCTRL(7, 2)
+#define	SBCTRL73		SBCTRL(7, 3)
+#define	SBCTRL74		(SBCTRL_BASE + 0x170)
+
+/* slower but LED works */
+#define SBCTRL0_SAVEPIN_PERI_VALUE	0x55450000
+#define SBCTRL1_SAVEPIN_PERI_VALUE	0x07168d00
+#define SBCTRL2_SAVEPIN_PERI_VALUE	0x34000009
+#define SBCTRL4_SAVEPIN_PERI_VALUE	0x02110110
+
+/* faster but LED does not work */
+#define SBCTRL0_SAVEPIN_MEM_VALUE	0x55450000
+#define SBCTRL1_SAVEPIN_MEM_VALUE	0x06057700
+/* NOR flash needs more wait counts than SRAM */
+#define SBCTRL2_SAVEPIN_MEM_VALUE	0x34000009
+#define SBCTRL4_SAVEPIN_MEM_VALUE	0x02110210
+
+#define SBCTRL0_ADMULTIPLX_PERI_VALUE	0x33120000
+#define SBCTRL1_ADMULTIPLX_PERI_VALUE	0x03005500
+#define SBCTRL2_ADMULTIPLX_PERI_VALUE	0x14000020
+
+#define SBCTRL0_ADMULTIPLX_MEM_VALUE	0x33120000
+#define SBCTRL1_ADMULTIPLX_MEM_VALUE	0x03005500
+#define SBCTRL2_ADMULTIPLX_MEM_VALUE	0x14000010
+
+#define ROM_BOOT_ROMRSV2		0x59801208
+
+#ifndef __ASSEMBLY__
+#include <asm/io.h>
+static inline int boot_is_swapped(void)
+{
+	return !(readl(SBBASE0) & SBBASE_BANK_ENABLE);
+}
+#endif
+
+#endif	/* ARCH_SBC_REGS_H */
diff --git a/arch/arm/include/asm/arch-uniphier/sc-regs.h b/arch/arm/include/asm/arch-uniphier/sc-regs.h
new file mode 100644
index 0000000..1197bb5
--- /dev/null
+++ b/arch/arm/include/asm/arch-uniphier/sc-regs.h
@@ -0,0 +1,62 @@
+/*
+ * UniPhier SC (System Control) block registers
+ *
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef ARCH_SC_REGS_H
+#define ARCH_SC_REGS_H
+
+#define SC_BASE_ADDR			0x61840000
+
+#define SC_MPLLOSCCTL                   (SC_BASE_ADDR | 0x1184)
+#define SC_MPLLOSCCTL_MPLLEN		(0x1 << 0)
+#define SC_MPLLOSCCTL_MPLLST		(0x1 << 1)
+
+#define SC_DPLLCTRL			(SC_BASE_ADDR | 0x1200)
+#define SC_DPLLCTRL_SSC_EN		(0x1 << 31)
+#define SC_DPLLCTRL_FOUTMODE_MASK        (0xf << 16)
+#define SC_DPLLCTRL_SSC_RATE		(0x1 << 15)
+
+#define SC_DPLLCTRL2			(SC_BASE_ADDR | 0x1204)
+#define SC_DPLLCTRL2_NRSTDS		(0x1 << 28)
+
+#define SC_DPLLCTRL3			(SC_BASE_ADDR | 0x1208)
+#define SC_DPLLCTRL3_LPFSEL_COEF2	(0x0 << 31)
+#define SC_DPLLCTRL3_LPFSEL_COEF3	(0x1 << 31)
+
+#define SC_UPLLCTRL			(SC_BASE_ADDR | 0x1210)
+
+#define SC_VPLL27ACTRL			(SC_BASE_ADDR | 0x1270)
+#define SC_VPLL27ACTRL2			(SC_BASE_ADDR | 0x1274)
+#define SC_VPLL27ACTRL3			(SC_BASE_ADDR | 0x1278)
+
+#define SC_VPLL27BCTRL			(SC_BASE_ADDR | 0x1290)
+#define SC_VPLL27BCTRL2			(SC_BASE_ADDR | 0x1294)
+#define SC_VPLL27BCTRL3			(SC_BASE_ADDR | 0x1298)
+
+#define SC_RSTCTRL			(SC_BASE_ADDR | 0x2000)
+#define SC_RSTCTRL_NRST_ETHER		(0x1 << 12)
+#define SC_RSTCTRL_NRST_UMC1		(0x1 <<  5)
+#define SC_RSTCTRL_NRST_UMC0		(0x1 <<  4)
+#define SC_RSTCTRL_NRST_NAND		(0x1 <<  2)
+
+#define SC_RSTCTRL2			(SC_BASE_ADDR | 0x2004)
+#define SC_RSTCTRL3			(SC_BASE_ADDR | 0x2008)
+
+#define SC_CLKCTRL			(SC_BASE_ADDR | 0x2104)
+#define SC_CLKCTRL_CLK_ETHER		(0x1 << 12)
+#define SC_CLKCTRL_CLK_MIO		(0x1 << 11)
+#define SC_CLKCTRL_CLK_UMC		(0x1 <<  4)
+#define SC_CLKCTRL_CLK_NAND		(0x1 <<  2)
+#define SC_CLKCTRL_CLK_SBC		(0x1 <<  1)
+#define SC_CLKCTRL_CLK_PERI		(0x1 <<  0)
+
+/* System reset control register */
+#define SC_IRQTIMSET			(SC_BASE_ADDR | 0x3000)
+#define SC_SLFRSTSEL			(SC_BASE_ADDR | 0x3010)
+#define SC_SLFRSTCTL			(SC_BASE_ADDR | 0x3014)
+
+#endif /* ARCH_SC_REGS_H */
diff --git a/arch/arm/include/asm/arch-uniphier/sg-regs.h b/arch/arm/include/asm/arch-uniphier/sg-regs.h
new file mode 100644
index 0000000..79d7ec7
--- /dev/null
+++ b/arch/arm/include/asm/arch-uniphier/sg-regs.h
@@ -0,0 +1,182 @@
+/*
+ * UniPhier SG (SoC Glue) block registers
+ *
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef ARCH_SG_REGS_H
+#define ARCH_SG_REGS_H
+
+/* Base Address */
+#define SG_CTRL_BASE			0x5f800000
+#define SG_DBG_BASE			0x5f900000
+
+/* Revision */
+#define SG_REVISION			(SG_CTRL_BASE | 0x0000)
+#define SG_REVISION_TYPE_SHIFT		16
+#define SG_REVISION_TYPE_MASK		(0xff << SG_REVISION_TYPE_SHIFT)
+#define SG_REVISION_MODEL_SHIFT		8
+#define SG_REVISION_MODEL_MASK		(0x3 << SG_REVISION_MODEL_SHIFT)
+#define SG_REVISION_REV_SHIFT		0
+#define SG_REVISION_REV_MASK		(0x1f << SG_REVISION_REV_SHIFT)
+
+/* Memory Configuration */
+#define SG_MEMCONF			(SG_CTRL_BASE | 0x0400)
+
+#define SG_MEMCONF_CH0_SIZE_64MB	((0x0 << 10) | (0x01 << 0))
+#define SG_MEMCONF_CH0_SIZE_128MB	((0x0 << 10) | (0x02 << 0))
+#define SG_MEMCONF_CH0_SIZE_256MB	((0x0 << 10) | (0x03 << 0))
+#define SG_MEMCONF_CH0_SIZE_512MB	((0x1 << 10) | (0x00 << 0))
+#define SG_MEMCONF_CH0_SIZE_1024MB	((0x1 << 10) | (0x01 << 0))
+#define SG_MEMCONF_CH0_NUM_1		(0x1 << 8)
+#define SG_MEMCONF_CH0_NUM_2		(0x0 << 8)
+
+#define SG_MEMCONF_CH1_SIZE_64MB	((0x0 << 11) | (0x01 << 2))
+#define SG_MEMCONF_CH1_SIZE_128MB	((0x0 << 11) | (0x02 << 2))
+#define SG_MEMCONF_CH1_SIZE_256MB	((0x0 << 11) | (0x03 << 2))
+#define SG_MEMCONF_CH1_SIZE_512MB	((0x1 << 11) | (0x00 << 2))
+#define SG_MEMCONF_CH1_SIZE_1024MB	((0x1 << 11) | (0x01 << 2))
+#define SG_MEMCONF_CH1_NUM_1		(0x1 << 9)
+#define SG_MEMCONF_CH1_NUM_2		(0x0 << 9)
+
+#define SG_MEMCONF_SPARSEMEM		(0x1 << 4)
+
+/* Pin Control */
+#define SG_PINCTRL_BASE			(SG_CTRL_BASE | 0x1000)
+
+#if defined(CONFIG_MACH_PH1_PRO4)
+# define SG_PINCTRL(n)			(SG_PINCTRL_BASE + (n) * 8)
+#elif defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
+# define SG_PINCTRL(n)			(SG_PINCTRL_BASE + (n) * 4)
+#endif
+
+#if defined(CONFIG_MACH_PH1_PRO4)
+#define SG_PINSELBITS			4
+#elif defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
+#define SG_PINSELBITS			8
+#endif
+
+#define SG_PINSEL_ADDR(n)		(SG_PINCTRL((n) * (SG_PINSELBITS) / 32))
+#define SG_PINSEL_MASK(n)		(~(((1 << (SG_PINSELBITS)) - 1) << \
+						((n) * (SG_PINSELBITS) % 32)))
+#define SG_PINSEL_MODE(n, mode)		((mode) << ((n) * (SG_PINSELBITS) % 32))
+
+/* Only for PH1-Pro4 */
+#define SG_LOADPINCTRL			(SG_CTRL_BASE | 0x1700)
+
+/* Input Enable */
+#define SG_IECTRL			(SG_CTRL_BASE | 0x1d00)
+
+/* Pin Monitor */
+#define SG_PINMON0			(SG_DBG_BASE | 0x0100)
+
+#define SG_PINMON0_CLK_MODE_UPLLSRC_MASK	(0x3 << 19)
+#define SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT	(0x0 << 19)
+#define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27A	(0x2 << 19)
+#define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27B	(0x3 << 19)
+
+#define SG_PINMON0_CLK_MODE_AXOSEL_MASK		(0x3 << 16)
+#define SG_PINMON0_CLK_MODE_AXOSEL_24576KHZ	(0x0 << 16)
+#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ	(0x1 << 16)
+#define SG_PINMON0_CLK_MODE_AXOSEL_6144KHZ	(0x2 << 16)
+#define SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ	(0x3 << 16)
+
+#define SG_PINMON0_CLK_MODE_AXOSEL_DEFAULT	(0x0 << 16)
+#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U	(0x1 << 16)
+#define SG_PINMON0_CLK_MODE_AXOSEL_20480KHZ	(0x2 << 16)
+#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A	(0x3 << 16)
+
+#ifndef __ASSEMBLY__
+#include <linux/types.h>
+#include <asm/io.h>
+
+static inline void sg_set_pinsel(int n, int value)
+{
+	writel((readl(SG_PINSEL_ADDR(n)) & SG_PINSEL_MASK(n))
+	       | SG_PINSEL_MODE(n, value), SG_PINSEL_ADDR(n));
+}
+
+static inline u32 sg_memconf_val_ch0(unsigned long size, int num)
+{
+	int size_mb = (size >> 20) / num;
+	u32 ret;
+
+	switch (size_mb) {
+	case 64:
+		ret = SG_MEMCONF_CH0_SIZE_64MB;
+		break;
+	case 128:
+		ret = SG_MEMCONF_CH0_SIZE_128MB;
+		break;
+	case 256:
+		ret = SG_MEMCONF_CH0_SIZE_256MB;
+		break;
+	case 512:
+		ret = SG_MEMCONF_CH0_SIZE_512MB;
+		break;
+	case 1024:
+		ret = SG_MEMCONF_CH0_SIZE_1024MB;
+		break;
+	default:
+		BUG();
+		break;
+	}
+
+	switch (num) {
+	case 1:
+		ret |= SG_MEMCONF_CH0_NUM_1;
+		break;
+	case 2:
+		ret |= SG_MEMCONF_CH0_NUM_2;
+		break;
+	default:
+		BUG();
+		break;
+	}
+	return ret;
+}
+
+static inline u32 sg_memconf_val_ch1(unsigned long size, int num)
+{
+	int size_mb = (size >> 20) / num;
+	u32 ret;
+
+	switch (size_mb) {
+	case 64:
+		ret = SG_MEMCONF_CH1_SIZE_64MB;
+		break;
+	case 128:
+		ret = SG_MEMCONF_CH1_SIZE_128MB;
+		break;
+	case 256:
+		ret = SG_MEMCONF_CH1_SIZE_256MB;
+		break;
+	case 512:
+		ret = SG_MEMCONF_CH1_SIZE_512MB;
+		break;
+	case 1024:
+		ret = SG_MEMCONF_CH1_SIZE_1024MB;
+		break;
+	default:
+		BUG();
+		break;
+	}
+
+	switch (num) {
+	case 1:
+		ret |= SG_MEMCONF_CH1_NUM_1;
+		break;
+	case 2:
+		ret |= SG_MEMCONF_CH1_NUM_2;
+		break;
+	default:
+		BUG();
+		break;
+	}
+	return ret;
+}
+#endif /* __ASSEMBLY__ */
+
+#endif /* ARCH_SG_REGS_H */
diff --git a/arch/arm/include/asm/arch-uniphier/ssc-regs.h b/arch/arm/include/asm/arch-uniphier/ssc-regs.h
new file mode 100644
index 0000000..77b3470
--- /dev/null
+++ b/arch/arm/include/asm/arch-uniphier/ssc-regs.h
@@ -0,0 +1,67 @@
+/*
+ * UniPhier System Cache (L2 Cache) registers
+ *
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef ARCH_SSC_REGS_H
+#define ARCH_SSC_REGS_H
+
+#define SSCC			0x500c0000
+#define SSCC_BST		(0x1 << 20)
+#define SSCC_ACT		(0x1 << 19)
+#define SSCC_WTG		(0x1 << 18)
+#define SSCC_PRD		(0x1 << 17)
+#define SSCC_WBWA		(0x1 << 16)
+#define SSCC_EX			(0x1 << 13)
+#define SSCC_ON			(0x1 <<  0)
+
+#define SSCLPDAWCR		0x500c0030
+
+#define SSCOPE			0x506c0244
+#define SSCOPE_CM_SYNC		0x00000008
+
+#define SSCOQM			0x506c0248
+#define SSCOQM_TID_MASK		(0x3 << 21)
+#define SSCOQM_TID_BY_WAY	(0x2 << 21)
+#define SSCOQM_TID_BY_INST_WAY	(0x1 << 21)
+#define SSCOQM_TID_BY_DATA_WAY	(0x0 << 21)
+#define SSCOQM_S_MASK		(0x3 << 17)
+#define SSCOQM_S_WAY		(0x2 << 17)
+#define SSCOQM_S_ALL		(0x1 << 17)
+#define SSCOQM_S_ADDRESS	(0x0 << 17)
+#define SSCOQM_CE		(0x1 << 15)
+#define SSCOQM_CW		(0x1 << 14)
+#define SSCOQM_CM_MASK		(0x7)
+#define SSCOQM_CM_DIRT_TOUCH	(0x7)
+#define SSCOQM_CM_ZERO_TOUCH	(0x6)
+#define SSCOQM_CM_NORM_TOUCH	(0x5)
+#define SSCOQM_CM_PREF_FETCH	(0x4)
+#define SSCOQM_CM_SSC_FETCH	(0x3)
+#define SSCOQM_CM_WB_INV	(0x2)
+#define SSCOQM_CM_WB		(0x1)
+#define SSCOQM_CM_INV		(0x0)
+
+#define SSCOQAD			0x506c024c
+#define SSCOQSZ			0x506c0250
+#define SSCOQWN			0x506c0258
+
+#define SSCOPPQSEF		0x506c025c
+#define SSCOPPQSEF_FE		(0x1 << 1)
+#define SSCOPPQSEF_OE		(0x1 << 0)
+
+#define SSCOLPQS		0x506c0260
+#define SSCOLPQS_EF		(0x1 << 2)
+#define SSCOLPQS_EST		(0x1 << 1)
+#define SSCOLPQS_QST		(0x1 << 0)
+
+#define SSCOQCE0		0x506c0270
+
+#define SSC_LINE_SIZE		128
+#define SSC_NUM_ENTRIES		256
+#define SSC_WAY_SIZE		((SSC_LINE_SIZE) * (SSC_NUM_ENTRIES))
+#define SSC_RANGE_OP_MAX_SIZE	(0x00400000 - (SSC_LINE_SIZE))
+
+#endif  /* ARCH_SSC_REGS_H */
diff --git a/arch/arm/include/asm/arch-uniphier/umc-regs.h b/arch/arm/include/asm/arch-uniphier/umc-regs.h
new file mode 100644
index 0000000..6159281
--- /dev/null
+++ b/arch/arm/include/asm/arch-uniphier/umc-regs.h
@@ -0,0 +1,119 @@
+/*
+ * UniPhier UMC (Universal Memory Controller) registers
+ *
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef ARCH_UMC_REGS_H
+#define ARCH_UMC_REGS_H
+
+#define UMC_BASE		0x5b800000
+
+/* SSIF registers */
+#define UMC_SSIF_BASE		UMC_BASE
+
+#define UMC_CPURST		0x00000700
+#define UMC_IDSRST		0x0000070C
+#define UMC_IXMRST		0x00000714
+#define UMC_HDMRST		0x00000718
+#define UMC_MDMRST		0x0000071C
+#define UMC_HDDRST		0x00000720
+#define UMC_MDDRST		0x00000724
+#define UMC_SIORST		0x00000728
+#define UMC_GIORST		0x0000072C
+#define UMC_HD2RST		0x00000734
+#define UMC_VIORST		0x0000073C
+#define UMC_FRCRST		0x00000748 /* LD4/sLD8 */
+#define UMC_DVCRST		0x00000748 /* Pro4 */
+#define UMC_RGLRST		0x00000750
+#define UMC_VPERST		0x00000758
+#define UMC_AIORST		0x00000764
+#define UMC_DMDRST		0x00000770
+
+#define UMC_HDMCHSEL		0x00000898
+#define UMC_MDMCHSEL		0x0000089C
+#define UMC_DVCCHSEL		0x000008C8
+#define UMC_DMDCHSEL		0x000008F0
+
+#define UMC_CLKEN_SSIF_FETCH	0x0000C060
+#define UMC_CLKEN_SSIF_COMQUE0	0x0000C064
+#define UMC_CLKEN_SSIF_COMWC0	0x0000C068
+#define UMC_CLKEN_SSIF_COMRC0	0x0000C06C
+#define UMC_CLKEN_SSIF_COMQUE1	0x0000C070
+#define UMC_CLKEN_SSIF_COMWC1	0x0000C074
+#define UMC_CLKEN_SSIF_COMRC1	0x0000C078
+#define UMC_CLKEN_SSIF_WC	0x0000C07C
+#define UMC_CLKEN_SSIF_RC	0x0000C080
+#define UMC_CLKEN_SSIF_DST	0x0000C084
+
+/* CA registers */
+#define UMC_CA_BASE(ch)		(UMC_BASE + 0x00001000 + 0x00001000 * (ch))
+
+/* DRAM controller registers */
+#define UMC_DRAMCONT_BASE(ch)	(UMC_BASE + 0x00400000 + 0x00200000 * (ch))
+
+#define UMC_CMDCTLA		0x00000000
+#define UMC_CMDCTLB		0x00000004
+#define UMC_INITCTLA		0x00000008
+#define UMC_INITCTLB		0x0000000C
+#define UMC_INITCTLC		0x00000010
+#define UMC_INITSET		0x00000014
+#define UMC_INITSTAT		0x00000018
+#define UMC_DRMMR0		0x0000001C
+#define UMC_DRMMR1		0x00000020
+#define UMC_DRMMR2		0x00000024
+#define UMC_DRMMR3		0x00000028
+#define UMC_SPCCTLA		0x00000030
+#define UMC_SPCCTLB		0x00000034
+#define UMC_SPCSETA		0x00000038
+#define UMC_SPCSETB		0x0000003C
+#define UMC_SPCSETC		0x00000040
+#define UMC_SPCSETD		0x00000044
+#define UMC_SPCSTATA		0x00000050
+#define UMC_SPCSTATB		0x00000054
+#define UMC_SPCSTATC		0x00000058
+#define UMC_ACSSETA		0x00000060
+#define UMC_FLOWCTLA		0x00000400
+#define UMC_FLOWCTLB		0x00000404
+#define UMC_FLOWCTLC		0x00000408
+#define UMC_FLOWCTLG		0x00000508
+#define UMC_RDATACTL_D0		0x00000600
+#define UMC_WDATACTL_D0		0x00000604
+#define UMC_RDATACTL_D1		0x00000608
+#define UMC_WDATACTL_D1		0x0000060C
+#define UMC_DATASET		0x00000610
+#define UMC_DCCGCTL		0x00000720
+#define UMC_DICGCTLA		0x00000724
+#define UMC_DICGCTLB		0x00000728
+#define UMC_DIOCTLA		0x00000C00
+#define UMC_DFICUPDCTLA		0x00000C20
+
+#ifndef __ASSEMBLY__
+
+#include <linux/types.h>
+
+static inline void umc_polling(u32 address, u32 expval, u32 mask)
+{
+	u32 nmask = ~mask;
+	u32 data;
+	do {
+		data = readl(address) & nmask;
+	} while (data != expval);
+}
+
+static inline void umc_dram_init_start(void __iomem *dramcont)
+{
+	writel(0x00000002, dramcont + UMC_INITSET);
+}
+
+static inline void umc_dram_init_poll(void __iomem *dramcont)
+{
+	while ((readl(dramcont + UMC_INITSTAT) & 0x00000002))
+		;
+}
+
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h
index bb00217..9d797db 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -103,9 +103,11 @@
 /* DDRMC */
 #define DDRMC_PHY_DQ_TIMING				0x00002613
 #define DDRMC_PHY_DQS_TIMING				0x00002615
-#define DDRMC_PHY_CTRL					0x01210080
+#define DDRMC_PHY_CTRL					0x00210000
 #define DDRMC_PHY_MASTER_CTRL				0x0001012a
-#define DDRMC_PHY_SLAVE_CTRL				0x00012020
+#define DDRMC_PHY_SLAVE_CTRL				0x00002000
+#define DDRMC_PHY_OFF					0x00000000
+#define DDRMC_PHY_PROC_PAD_ODT				0x00010101
 
 #define DDRMC_PHY50_DDR3_MODE				(1 << 12)
 #define DDRMC_PHY50_EN_SW_HALF_CYCLE			(1 << 8)
@@ -138,7 +140,7 @@
 #define DDRMC_CR21_CCMAP_EN				1
 #define DDRMC_CR22_TDAL(v)				(((v) & 0x3f) << 16)
 #define DDRMC_CR23_BSTLEN(v)				(((v) & 0x7) << 24)
-#define DDRMC_CR23_TDLL(v)				((v) & 0xff)
+#define DDRMC_CR23_TDLL(v)				((v) & 0xffff)
 #define DDRMC_CR24_TRP_AB(v)				((v) & 0x1f)
 #define DDRMC_CR25_TREF_EN				(1 << 16)
 #define DDRMC_CR26_TREF(v)				(((v) & 0xffff) << 16)
@@ -151,7 +153,7 @@
 #define DDRMC_CR33_EN_QK_SREF				(1 << 16)
 #define DDRMC_CR34_CKSRX(v)				(((v) & 0xf) << 16)
 #define DDRMC_CR34_CKSRE(v)				(((v) & 0xf) << 8)
-#define DDRMC_CR38_FREQ_CHG_EN				(1 << 8)
+#define DDRMC_CR38_FREQ_CHG_EN(v)			(((v) & 0x1) << 8)
 #define DDRMC_CR39_PHY_INI_COM(v)			(((v) & 0xffff) << 16)
 #define DDRMC_CR39_PHY_INI_STA(v)			(((v) & 0xff) << 8)
 #define DDRMC_CR39_FRQ_CH_DLLOFF(v)			((v) & 0x3)
@@ -163,7 +165,7 @@
 #define DDRMC_CR67_ZQCS(v)				((v) & 0xfff)
 #define DDRMC_CR69_ZQ_ON_SREF_EX(v)			(((v) & 0xf) << 8)
 #define DDRMC_CR70_REF_PER_ZQ(v)			(v)
-#define DDRMC_CR72_ZQCS_ROTATE				(1 << 24)
+#define DDRMC_CR72_ZQCS_ROTATE(v)			(((v) & 0x1) << 24)
 #define DDRMC_CR73_APREBIT(v)				(((v) & 0xf) << 24)
 #define DDRMC_CR73_COL_DIFF(v)				(((v) & 0x7) << 16)
 #define DDRMC_CR73_ROW_DIFF(v)				(((v) & 0x3) << 8)
@@ -182,9 +184,10 @@
 #define DDRMC_CR77_CS_MAP				(1 << 24)
 #define DDRMC_CR77_DI_RD_INTLEAVE			(1 << 8)
 #define DDRMC_CR77_SWAP_EN				1
+#define DDRMC_CR78_Q_FULLNESS(v)			(((v) & 0x7) << 24)
 #define DDRMC_CR78_BUR_ON_FLY_BIT(v)			((v) & 0xf)
-#define DDRMC_CR79_CTLUPD_AREF				(1 << 24)
-#define DDRMC_CR82_INT_MASK				0x1fffffff
+#define DDRMC_CR79_CTLUPD_AREF(v)			(((v) & 0x1) << 24)
+#define DDRMC_CR82_INT_MASK				0x10000000
 #define DDRMC_CR87_ODT_WR_MAPCS0			(1 << 24)
 #define DDRMC_CR87_ODT_RD_MAPCS0			(1 << 16)
 #define DDRMC_CR88_TODTL_CMD(v)				(((v) & 0x1f) << 16)
@@ -192,9 +195,17 @@
 #define DDRMC_CR91_R2W_SMCSDL(v)			(((v) & 0x7) << 16)
 #define DDRMC_CR96_WLMRD(v)				(((v) & 0x3f) << 8)
 #define DDRMC_CR96_WLDQSEN(v)				((v) & 0x3f)
+#define DDRMC_CR97_WRLVL_EN				(1 << 24)
+#define DDRMC_CR98_WRLVL_DL_0				(0)
+#define DDRMC_CR99_WRLVL_DL_1				(0)
+#define DDRMC_CR102_RDLVL_GT_REGEN			(1 << 16)
+#define DDRMC_CR102_RDLVL_REG_EN			(1 << 8)
 #define DDRMC_CR105_RDLVL_DL_0(v)			(((v) & 0xff) << 8)
+#define DDRMC_CR106_RDLVL_GTDL_0(v)			((v) & 0xff)
 #define DDRMC_CR110_RDLVL_DL_1(v)			((v) & 0xff)
+#define DDRMC_CR110_RDLVL_GTDL_1(v)			(((v) & 0xff) << 16)
 #define DDRMC_CR114_RDLVL_GTDL_2(v)			(((v) & 0xffff) << 8)
+#define DDRMC_CR115_RDLVL_GTDL_2(v)			((v) & 0xff)
 #define DDRMC_CR117_AXI0_W_PRI(v)			(((v) & 0x3) << 8)
 #define DDRMC_CR117_AXI0_R_PRI(v)			((v) & 0x3)
 #define DDRMC_CR118_AXI1_W_PRI(v)			(((v) & 0x3) << 24)
@@ -208,20 +219,42 @@
 #define DDRMC_CR122_AXI0_PRIRLX(v)			((v) & 0x3ff)
 #define DDRMC_CR123_AXI1_PRI3_RPRI(v)			(((v) & 0xf) << 8)
 #define DDRMC_CR123_AXI1_PRI2_RPRI(v)			((v) & 0xf)
+#define DDRMC_CR123_AXI1_P_ODR_EN			(1 << 16)
 #define DDRMC_CR124_AXI1_PRIRLX(v)			((v) & 0x3ff)
 #define DDRMC_CR126_PHY_RDLAT(v)			(((v) & 0x3f) << 8)
 #define DDRMC_CR132_WRLAT_ADJ(v)			(((v) & 0x1f) << 8)
 #define DDRMC_CR132_RDLAT_ADJ(v)			((v) & 0x3f)
+#define DDRMC_CR137_PHYCTL_DL(v)			(((v) & 0xf) << 16)
+#define DDRMC_CR138_PHY_WRLV_MXDL(v)			(((v) & 0xffff) << 16)
+#define DDRMC_CR138_PHYDRAM_CK_EN(v)			(((v) & 0x8) << 8)
 #define DDRMC_CR139_PHY_WRLV_RESPLAT(v)			(((v) & 0xff) << 24)
 #define DDRMC_CR139_PHY_WRLV_LOAD(v)			(((v) & 0xff) << 16)
 #define DDRMC_CR139_PHY_WRLV_DLL(v)			(((v) & 0xff) << 8)
 #define DDRMC_CR139_PHY_WRLV_EN(v)			((v) & 0xff)
+#define DDRMC_CR140_PHY_WRLV_WW(v)			((v) & 0x3ff)
+#define DDRMC_CR143_RDLV_GAT_MXDL(v)			(((v) & 0xffff) << 16)
+#define DDRMC_CR143_RDLV_MXDL(v)			((v) & 0xffff)
+#define DDRMC_CR144_PHY_RDLVL_RES(v)			(((v) & 0xff) << 24)
+#define DDRMC_CR144_PHY_RDLV_LOAD(v)			(((v) & 0xff) << 16)
+#define DDRMC_CR144_PHY_RDLV_DLL(v)			(((v) & 0xff) << 8)
+#define DDRMC_CR144_PHY_RDLV_EN(v)			((v) & 0xff)
+#define DDRMC_CR145_PHY_RDLV_RR(v)			((v) & 0x3ff)
+#define DDRMC_CR146_PHY_RDLVL_RESP(v)			(v)
+#define DDRMC_CR147_RDLV_RESP_MASK(v)			((v) & 0xfffff)
+#define DDRMC_CR148_RDLV_GATE_RESP_MASK(v)		((v) & 0xfffff)
+#define DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(v)		(((v) & 0xf) << 8)
+#define DDRMC_CR151_RDLVL_DQ_ZERO_CNT(v)		((v) & 0xf)
 #define DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(v)	(((v) & 0x1f) << 27)
 #define DDRMC_CR154_PAD_ZQ_MODE(v)			(((v) & 0x3) << 21)
 #define DDRMC_CR154_DDR_SEL_PAD_CONTR(v)		(((v) & 0x3) << 18)
+#define DDRMC_CR154_PAD_ZQ_HW_FOR(v)			(((v) & 0x1) << 14)
 #define DDRMC_CR155_AXI0_AWCACHE			(1 << 10)
-#define DDRMC_CR155_PAD_ODT_BYTE1(v)			((v) & 0x7)
+#define DDRMC_CR155_PAD_ODT_BYTE1(v)			(((v) & 0x7) << 3)
+#define DDRMC_CR155_PAD_ODT_BYTE0(v)			((v) & 0x7)
 #define DDRMC_CR158_TWR(v)				((v) & 0x3f)
+#define DDRMC_CR161_ODT_EN(v)				(((v) & 0x1) << 16)
+#define DDRMC_CR161_TODTH_RD(v)				(((v) & 0xf) << 8)
+#define DDRMC_CR161_TODTH_WR(v)				((v) & 0xf)
 
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
 #include <asm/types.h>
diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h
index 7464da8..9226e69 100644
--- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h
+++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h
@@ -17,6 +17,8 @@
 #define VF610_ENET_PAD_CTRL	(PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \
 				PAD_CTL_OBE_IBE_ENABLE)
 #define VF610_DDR_PAD_CTRL	PAD_CTL_DSE_25ohm
+#define VF610_DDR_PAD_CTRL_1	(PAD_CTL_DSE_25ohm | \
+				PAD_CTL_INPUT_DIFFERENTIAL)
 #define VF610_I2C_PAD_CTRL	(PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \
 				PAD_CTL_SPEED_HIGH | PAD_CTL_OBE_IBE_ENABLE)
 #define VF610_NFC_IO_PAD_CTRL	(PAD_CTL_SPEED_MED | PAD_CTL_SRE | \
@@ -102,6 +104,7 @@ enum {
 
 	VF610_PAD_PTC28__NF_CLE  		= IOMUX_PAD(0x0194, 0x0194, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
 
+	VF610_PAD_DDR_RESETB			= IOMUX_PAD(0x021c, 0x021c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
 	VF610_PAD_DDR_A15__DDR_A_15		= IOMUX_PAD(0x0220, 0x0220, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
 	VF610_PAD_DDR_A14__DDR_A_14		= IOMUX_PAD(0x0224, 0x0224, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
 	VF610_PAD_DDR_A13__DDR_A_13		= IOMUX_PAD(0x0228, 0x0228, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
@@ -117,6 +120,7 @@ enum {
 	VF610_PAD_DDR_A3__DDR_A_3		= IOMUX_PAD(0x0250, 0x0250, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
 	VF610_PAD_DDR_A2__DDR_A_2		= IOMUX_PAD(0x0254, 0x0254, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
 	VF610_PAD_DDR_A1__DDR_A_1		= IOMUX_PAD(0x0258, 0x0258, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_A0__DDR_A_0		= IOMUX_PAD(0x025c, 0x025c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
 	VF610_PAD_DDR_BA2__DDR_BA_2		= IOMUX_PAD(0x0260, 0x0260, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
 	VF610_PAD_DDR_BA1__DDR_BA_1		= IOMUX_PAD(0x0264, 0x0264, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
 	VF610_PAD_DDR_BA0__DDR_BA_0		= IOMUX_PAD(0x0268, 0x0268, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
@@ -124,26 +128,26 @@ enum {
 	VF610_PAD_DDR_CKE__DDR_CKE_0		= IOMUX_PAD(0x0270, 0x0270, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
 	VF610_PAD_DDR_CLK__DDR_CLK_0		= IOMUX_PAD(0x0274, 0x0274, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
 	VF610_PAD_DDR_CS__DDR_CS_B_0		= IOMUX_PAD(0x0278, 0x0278, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_D15__DDR_D_15		= IOMUX_PAD(0x027c, 0x027c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_D14__DDR_D_14		= IOMUX_PAD(0x0280, 0x0280, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_D13__DDR_D_13		= IOMUX_PAD(0x0284, 0x0284, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_D12__DDR_D_12		= IOMUX_PAD(0x0288, 0x0288, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_D11__DDR_D_11		= IOMUX_PAD(0x028c, 0x028c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_D10__DDR_D_10		= IOMUX_PAD(0x0290, 0x0290, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_D9__DDR_D_9		= IOMUX_PAD(0x0294, 0x0294, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_D8__DDR_D_8		= IOMUX_PAD(0x0298, 0x0298, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_D7__DDR_D_7		= IOMUX_PAD(0x029c, 0x029c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_D6__DDR_D_6		= IOMUX_PAD(0x02a0, 0x02a0, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_D5__DDR_D_5		= IOMUX_PAD(0x02a4, 0x02a4, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_D4__DDR_D_4		= IOMUX_PAD(0x02a8, 0x02a8, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_D3__DDR_D_3		= IOMUX_PAD(0x02ac, 0x02ac, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_D2__DDR_D_2		= IOMUX_PAD(0x02b0, 0x02b0, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_D1__DDR_D_1		= IOMUX_PAD(0x02b4, 0x02b4, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_D0__DDR_D_0		= IOMUX_PAD(0x02b8, 0x02b8, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_DQM1__DDR_DQM_1		= IOMUX_PAD(0x02bc, 0x02bc, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_DQM0__DDR_DQM_0		= IOMUX_PAD(0x02c0, 0x02c0, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_DQS1__DDR_DQS_1		= IOMUX_PAD(0x02c4, 0x02c4, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_DQS0__DDR_DQS_0		= IOMUX_PAD(0x02c8, 0x02c8, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_D15__DDR_D_15		= IOMUX_PAD(0x027c, 0x027c, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+	VF610_PAD_DDR_D14__DDR_D_14		= IOMUX_PAD(0x0280, 0x0280, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+	VF610_PAD_DDR_D13__DDR_D_13		= IOMUX_PAD(0x0284, 0x0284, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+	VF610_PAD_DDR_D12__DDR_D_12		= IOMUX_PAD(0x0288, 0x0288, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+	VF610_PAD_DDR_D11__DDR_D_11		= IOMUX_PAD(0x028c, 0x028c, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+	VF610_PAD_DDR_D10__DDR_D_10		= IOMUX_PAD(0x0290, 0x0290, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+	VF610_PAD_DDR_D9__DDR_D_9		= IOMUX_PAD(0x0294, 0x0294, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+	VF610_PAD_DDR_D8__DDR_D_8		= IOMUX_PAD(0x0298, 0x0298, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+	VF610_PAD_DDR_D7__DDR_D_7		= IOMUX_PAD(0x029c, 0x029c, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+	VF610_PAD_DDR_D6__DDR_D_6		= IOMUX_PAD(0x02a0, 0x02a0, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+	VF610_PAD_DDR_D5__DDR_D_5		= IOMUX_PAD(0x02a4, 0x02a4, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+	VF610_PAD_DDR_D4__DDR_D_4		= IOMUX_PAD(0x02a8, 0x02a8, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+	VF610_PAD_DDR_D3__DDR_D_3		= IOMUX_PAD(0x02ac, 0x02ac, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+	VF610_PAD_DDR_D2__DDR_D_2		= IOMUX_PAD(0x02b0, 0x02b0, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+	VF610_PAD_DDR_D1__DDR_D_1		= IOMUX_PAD(0x02b4, 0x02b4, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+	VF610_PAD_DDR_D0__DDR_D_0		= IOMUX_PAD(0x02b8, 0x02b8, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+	VF610_PAD_DDR_DQM1__DDR_DQM_1		= IOMUX_PAD(0x02bc, 0x02bc, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+	VF610_PAD_DDR_DQM0__DDR_DQM_0		= IOMUX_PAD(0x02c0, 0x02c0, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+	VF610_PAD_DDR_DQS1__DDR_DQS_1		= IOMUX_PAD(0x02c4, 0x02c4, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+	VF610_PAD_DDR_DQS0__DDR_DQS_0		= IOMUX_PAD(0x02c8, 0x02c8, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
 	VF610_PAD_DDR_RAS__DDR_RAS_B		= IOMUX_PAD(0x02cc, 0x02cc, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
 	VF610_PAD_DDR_WE__DDR_WE_B		= IOMUX_PAD(0x02d0, 0x02d0, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
 	VF610_PAD_DDR_ODT1__DDR_ODT_0		= IOMUX_PAD(0x02d4, 0x02d4, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h
index 70ee86c..a8ca49c 100644
--- a/arch/arm/include/asm/imx-common/iomux-v3.h
+++ b/arch/arm/include/asm/imx-common/iomux-v3.h
@@ -120,6 +120,8 @@ typedef u64 iomux_v3_cfg_t;
 
 #define PAD_MUX_MODE_SHIFT	20
 
+#define PAD_CTL_INPUT_DIFFERENTIAL (1 << 16)
+
 #define PAD_CTL_SPEED_MED	(1 << 12)
 #define PAD_CTL_SPEED_HIGH	(3 << 12)