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| author | Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> | 2015-06-26 18:05:07 +0530 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2015-07-31 01:38:12 +0200 |
| commit | dad17fd51027ad02ac8f02deed186d08109d61fd (patch) | |
| tree | ef4f7170fbea6995436173711b2d23e65b07bdb0 /arch/arm/include/asm | |
| parent | cc35734358540a1bbaf042fdf9f4cb2de17389ed (diff) | |
| download | u-boot-imx-dad17fd51027ad02ac8f02deed186d08109d61fd.zip u-boot-imx-dad17fd51027ad02ac8f02deed186d08109d61fd.tar.gz u-boot-imx-dad17fd51027ad02ac8f02deed186d08109d61fd.tar.bz2 | |
armv8: caches: Added routine to set non cacheable region
Added routine mmu_set_region_dcache_behaviour() to set a
particular region as non cacheable.
Define dummy routine for mmu_set_region_dcache_behaviour()
to handle incase of dcache off.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm/include/asm')
| -rw-r--r-- | arch/arm/include/asm/system.h | 29 |
1 files changed, 19 insertions, 10 deletions
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 760e8ab..868ea54 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -15,9 +15,15 @@ #define CR_EE (1 << 25) /* Exception (Big) Endian */ #define PGTABLE_SIZE (0x10000) +/* 2MB granularity */ +#define MMU_SECTION_SHIFT 21 #ifndef __ASSEMBLY__ +enum dcache_option { + DCACHE_OFF = 0x3, +}; + #define isb() \ ({asm volatile( \ "isb" : : : "memory"); \ @@ -265,16 +271,6 @@ enum { #endif /** - * Change the cache settings for a region. - * - * \param start start address of memory region to change - * \param size size of memory region to change - * \param option dcache option to select - */ -void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, - enum dcache_option option); - -/** * Register an update to the page tables, and flush the TLB * * \param start start address of update in page table @@ -295,4 +291,17 @@ phys_addr_t noncached_alloc(size_t size, size_t align); #endif /* CONFIG_ARM64 */ +#ifndef __ASSEMBLY__ +/** + * Change the cache settings for a region. + * + * \param start start address of memory region to change + * \param size size of memory region to change + * \param option dcache option to select + */ +void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, + enum dcache_option option); + +#endif /* __ASSEMBLY__ */ + #endif |