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| author | Tom Rini <trini@ti.com> | 2015-01-02 07:42:58 -0500 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2015-01-02 07:42:58 -0500 |
| commit | b4a0b4006fe4d6542899abf402c0569b11aa18e2 (patch) | |
| tree | 2b2916db1ec8ee619b4435167c5e1a0a4a274e02 /arch/arm/include/asm | |
| parent | a74a4a86a53726ba17de8ab863bec1cd60cf545e (diff) | |
| parent | be2fde60b0de7723d29035ba952a970d9e1ca94d (diff) | |
| download | u-boot-imx-b4a0b4006fe4d6542899abf402c0569b11aa18e2.zip u-boot-imx-b4a0b4006fe4d6542899abf402c0569b11aa18e2.tar.gz u-boot-imx-b4a0b4006fe4d6542899abf402c0569b11aa18e2.tar.bz2 | |
Merge branch 'master' of git://git.denx.de/u-boot-spi
Diffstat (limited to 'arch/arm/include/asm')
| -rw-r--r-- | arch/arm/include/asm/arch-mx6/clock.h | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx6/imx-regs.h | 12 |
2 files changed, 7 insertions, 6 deletions
diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index 226a4cd..a6de5ee 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -67,5 +67,6 @@ int enable_spi_clk(unsigned char enable, unsigned spi_num); void enable_ipu_clock(void); int enable_fec_anatop_clock(enum enet_freq freq); void enable_enet_clk(unsigned char enable); +void enable_qspi_clk(int qspi_num); void enable_thermal_clk(void); #endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 5314298..c968600 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -92,10 +92,10 @@ #define AIPS3_END_ADDR 0x022FFFFF #define WEIM_ARB_BASE_ADDR 0x50000000 #define WEIM_ARB_END_ADDR 0x57FFFFFF -#define QSPI1_ARB_BASE_ADDR 0x60000000 -#define QSPI1_ARB_END_ADDR 0x6FFFFFFF -#define QSPI2_ARB_BASE_ADDR 0x70000000 -#define QSPI2_ARB_END_ADDR 0x7FFFFFFF +#define QSPI0_AMBA_BASE 0x60000000 +#define QSPI0_AMBA_END 0x6FFFFFFF +#define QSPI1_AMBA_BASE 0x70000000 +#define QSPI1_AMBA_END 0x7FFFFFFF #else #define SATA_ARB_BASE_ADDR 0x02200000 #define SATA_ARB_END_ADDR 0x02203FFF @@ -262,8 +262,8 @@ #define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000) #ifdef CONFIG_MX6SX #define SAI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) -#define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) -#define QSPI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) +#define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) +#define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) #else #define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) #define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) |