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authorLokesh Vutla <lokeshvutla@ti.com>2015-02-16 10:15:56 +0530
committerTom Rini <trini@ti.com>2015-02-16 12:41:40 -0500
commit802bb57a584db2202a47d41ac730fe76ddeb4f33 (patch)
tree499ccc1cbbb52182227112a9fb7eb37fc7bfafe9 /arch/arm/include/asm
parentaa8ac43645243b69faf0e81fab5f0d6fcf4285cf (diff)
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ARM: DRA7: EMIF: Update SDRAM_REF_CTRL register value
The value in SDRAM_REF_CTRL controls the delay time between the initial rising edge of DDR_RESETn to rising edge of DDR_CKE (JEDEC specs this as 500us). In order to achieve this, SDRAM_REF_CTRL should be written with a value corresponding to 500us delay before starting DDR initialization sequence, and configure proper value at the end of sequence. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch/arm/include/asm')
-rw-r--r--arch/arm/include/asm/emif.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index 342f045..7a545ea 100644
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -1149,6 +1149,7 @@ struct emif_regs {
u32 sdram_config;
u32 sdram_config2;
u32 ref_ctrl;
+ u32 ref_ctrl_final;
u32 sdram_tim1;
u32 sdram_tim2;
u32 sdram_tim3;