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authorLokesh Vutla <lokeshvutla@ti.com>2015-06-03 14:43:21 +0530
committerTom Rini <trini@konsulko.com>2015-06-12 12:43:06 -0400
commit6213db78f4820816fc52c807dfab47bb3266c809 (patch)
tree9d6376a887b2da4f3db2b2eff83651a385e96fd2 /arch/arm/include/asm
parent9d01b7872e8fc5faa04e0fc2e33dbea02475d8c7 (diff)
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ARM: DRA7: DDR3: Add support for HW leveling
DRA7 EMIF supports Full leveling for DDR3. Adding support for the Full leveling sequence. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/include/asm')
-rw-r--r--arch/arm/include/asm/emif.h9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index 7a545ea..a97d2fd 100644
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -44,6 +44,8 @@
#define EMIF_REG_DUAL_CLK_MODE_MASK (1 << 30)
#define EMIF_REG_FAST_INIT_SHIFT 29
#define EMIF_REG_FAST_INIT_MASK (1 << 29)
+#define EMIF_REG_LEVLING_TO_SHIFT 4
+#define EMIF_REG_LEVELING_TO_MASK (7 << 4)
#define EMIF_REG_PHY_DLL_READY_SHIFT 2
#define EMIF_REG_PHY_DLL_READY_MASK (1 << 2)
@@ -509,6 +511,13 @@
#define EMIF_REG_RDWRLVLINC_RMP_WIN_SHIFT 0
#define EMIF_REG_RDWRLVLINC_RMP_WIN_MASK (0x1FFF << 0)
+/* EMIF_PHY_CTRL_36 */
+#define EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR (1 << 8)
+
+#define PHY_RDDQS_RATIO_REGS 5
+#define PHY_FIFO_WE_SLAVE_RATIO_REGS 5
+#define PHY_REG_WR_DQ_SLAVE_RATIO_REGS 10
+
/*Leveling Fields */
#define DDR3_WR_LVL_INT 0x73
#define DDR3_RD_LVL_INT 0x33