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| author | Hans de Goede <hdegoede@redhat.com> | 2014-11-30 11:58:17 +0100 |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2015-01-14 14:56:37 +0100 |
| commit | 5af741f1e98457de626f01302138de20c948fd46 (patch) | |
| tree | a77fa4b5708c5b5e5534e674073c86f4992e62ad /arch/arm/include/asm | |
| parent | d3a96f7a688c63883ed135518a8757b8c57f1f7b (diff) | |
| download | u-boot-imx-5af741f1e98457de626f01302138de20c948fd46.zip u-boot-imx-5af741f1e98457de626f01302138de20c948fd46.tar.gz u-boot-imx-5af741f1e98457de626f01302138de20c948fd46.tar.bz2 | |
sun6i: Add a sigma_delta_enable paramter to clock_set_pll5()
The sun8i dram code sometimes wants to enable sigma delta mode,
add a parameter to allow this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Diffstat (limited to 'arch/arm/include/asm')
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/clock.h | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 5 |
2 files changed, 5 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h index 64acff3..505c363 100644 --- a/arch/arm/include/asm/arch-sunxi/clock.h +++ b/arch/arm/include/asm/arch-sunxi/clock.h @@ -26,7 +26,6 @@ int clock_init(void); int clock_twi_onoff(int port, int state); void clock_set_pll1(unsigned int hz); void clock_set_pll3(unsigned int hz); -void clock_set_pll5(unsigned int hz); unsigned int clock_get_pll5p(void); unsigned int clock_get_pll6(void); void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz); diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index 3d4fcd1..f807af3 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -185,6 +185,7 @@ struct sunxi_ccm_reg { #define CCM_PLL5_CTRL_K(n) ((((n) - 1) & 0x3) << 4) #define CCM_PLL5_CTRL_N(n) ((((n) - 1) & 0x1f) << 8) #define CCM_PLL5_CTRL_UPD (0x1 << 20) +#define CCM_PLL5_CTRL_SIGMA_DELTA_EN (0x1 << 24) #define CCM_PLL5_CTRL_EN (0x1 << 31) #define PLL6_CFG_DEFAULT 0x90041811 /* 600 MHz */ @@ -274,6 +275,8 @@ struct sunxi_ccm_reg { #define MBUS_CLK_DEFAULT 0x81000001 /* PLL6 / 2 */ +#define CCM_PLL5_PATTERN 0xd1303333 + /* ahb_reset0 offsets */ #define AHB_RESET_OFFSET_GMAC 17 #define AHB_RESET_OFFSET_MCTL 14 @@ -308,4 +311,6 @@ struct sunxi_ccm_reg { #define CCM_DE_CTRL_PLL10 (5 << 24) #define CCM_DE_CTRL_GATE (1 << 31) +void clock_set_pll5(unsigned int clk, bool sigma_delta_enable); + #endif /* _SUNXI_CLOCK_SUN6I_H */ |