Merge git://git.denx.de/u-boot-marvell

3 files changed, 0 insertions, 266 deletions

diff --git a/arch/arm/include/asm/arch-armada-xp/config.h b/arch/arm/include/asm/arch-armada-xp/config.h
deleted file mode 100644
index f9fd424..0000000
--- a/arch/arm/include/asm/arch-armada-xp/config.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * This file should be included in board config header file.
- *
- * It supports common definitions for Armada XP platforms
- */
-
-#ifndef _ARMADA_XP_CONFIG_H
-#define _ARMADA_XP_CONFIG_H
-
-#include <asm/arch/soc.h>
-
-#define MV88F78X60 /* for the DDR training bin_hdr code */
-
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
-/*
- * By default kwbimage.cfg from board specific folder is used
- * If for some board, different configuration file need to be used,
- * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
- */
-#ifndef CONFIG_SYS_KWD_CONFIG
-#define	CONFIG_SYS_KWD_CONFIG	$(CONFIG_BOARDDIR)/kwbimage.cfg
-#endif /* CONFIG_SYS_KWD_CONFIG */
-
-/* Add target to build it automatically upon "make" */
-#ifdef CONFIG_SPL
-#define CONFIG_BUILD_TARGET	"u-boot-spl.kwb"
-#else
-#define CONFIG_BUILD_TARGET	"u-boot.kwb"
-#endif
-
-/* end of 16M scrubbed by training in bootrom */
-#define CONFIG_SYS_INIT_SP_ADDR		0x00FF0000
-#define CONFIG_NR_DRAM_BANKS_MAX	2
-
-#define MV_UART_CONSOLE_BASE		MVEBU_UART0_BASE
-
-/*
- * SPI Flash configuration
- */
-#ifdef CONFIG_CMD_SF
-#define CONFIG_HARD_SPI			1
-#define CONFIG_KIRKWOOD_SPI		1
-#ifndef CONFIG_ENV_SPI_BUS
-# define CONFIG_ENV_SPI_BUS		0
-#endif
-#ifndef CONFIG_ENV_SPI_CS
-# define CONFIG_ENV_SPI_CS		0
-#endif
-#ifndef CONFIG_ENV_SPI_MAX_HZ
-# define CONFIG_ENV_SPI_MAX_HZ		50000000
-#endif
-#endif
-
-/*
- * Ethernet Driver configuration
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_CMD_MII
-#define CONFIG_MII		/* expose smi ove miiphy interface */
-#define CONFIG_MVNETA		/* Enable Marvell Gbe Controller Driver */
-#define CONFIG_PHYLIB
-#define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
-#define CONFIG_PHY_GIGE		/* GbE speed/duplex detect */
-#endif /* CONFIG_CMD_NET */
-
-/*
- * I2C related stuff
- */
-#ifdef CONFIG_CMD_I2C
-#ifndef CONFIG_SYS_I2C_SOFT
-#define CONFIG_I2C_MVTWSI
-#endif
-#define CONFIG_SYS_I2C_SLAVE		0x0
-#define CONFIG_SYS_I2C_SPEED		100000
-#endif
-
-#endif /* _ARMADA_XP_CONFIG_H */
diff --git a/arch/arm/include/asm/arch-armada-xp/cpu.h b/arch/arm/include/asm/arch-armada-xp/cpu.h
deleted file mode 100644
index 4f5ff96..0000000
--- a/arch/arm/include/asm/arch-armada-xp/cpu.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _ARMADA_XP_CPU_H
-#define _ARMADA_XP_CPU_H
-
-#include <asm/system.h>
-
-#ifndef __ASSEMBLY__
-
-#define MVEBU_REG_PCIE_DEVID		(MVEBU_REG_PCIE_BASE + 0x00)
-#define MVEBU_REG_PCIE_REVID		(MVEBU_REG_PCIE_BASE + 0x08)
-
-enum memory_bank {
-	BANK0,
-	BANK1,
-	BANK2,
-	BANK3
-};
-
-enum cpu_winen {
-	CPU_WIN_DISABLE,
-	CPU_WIN_ENABLE
-};
-
-enum cpu_target {
-	CPU_TARGET_DRAM = 0x0,
-	CPU_TARGET_DEVICEBUS_BOOTROM_SPI = 0x1,
-	CPU_TARGET_ETH23 = 0x3,
-	CPU_TARGET_PCIE02 = 0x4,
-	CPU_TARGET_ETH01 = 0x7,
-	CPU_TARGET_PCIE13 = 0x8,
-	CPU_TARGET_SASRAM = 0x9,
-	CPU_TARGET_NAND = 0xd,
-};
-
-enum cpu_attrib {
-	CPU_ATTR_SASRAM = 0x01,
-	CPU_ATTR_DRAM_CS0 = 0x0e,
-	CPU_ATTR_DRAM_CS1 = 0x0d,
-	CPU_ATTR_DRAM_CS2 = 0x0b,
-	CPU_ATTR_DRAM_CS3 = 0x07,
-	CPU_ATTR_NANDFLASH = 0x2f,
-	CPU_ATTR_SPIFLASH = 0x1e,
-	CPU_ATTR_BOOTROM = 0x1d,
-	CPU_ATTR_PCIE_IO = 0xe0,
-	CPU_ATTR_PCIE_MEM = 0xe8,
-	CPU_ATTR_DEV_CS0 = 0x3e,
-	CPU_ATTR_DEV_CS1 = 0x3d,
-	CPU_ATTR_DEV_CS2 = 0x3b,
-	CPU_ATTR_DEV_CS3 = 0x37,
-};
-
-/*
- * Default Device Address MAP BAR values
- */
-#define DEFADR_PCI_MEM		0x90000000
-#define DEFADR_PCI_IO		0xC0000000
-#define DEFADR_SPIF		0xF4000000
-#define DEFADR_BOOTROM		0xF8000000
-
-struct mbus_win {
-	u32 base;
-	u32 size;
-	u8 target;
-	u8 attr;
-};
-
-/*
- * System registers
- * Ref: Datasheet sec:A.28
- */
-struct mvebu_system_registers {
-	u8 pad1[0x60];
-	u32 rstoutn_mask; /* 0x60 */
-	u32 sys_soft_rst; /* 0x64 */
-};
-
-/*
- * GPIO Registers
- * Ref: Datasheet sec:A.19
- */
-struct kwgpio_registers {
-	u32 dout;
-	u32 oe;
-	u32 blink_en;
-	u32 din_pol;
-	u32 din;
-	u32 irq_cause;
-	u32 irq_mask;
-	u32 irq_level;
-};
-
-/* Needed for dynamic (board-specific) mbus configuration */
-extern struct mvebu_mbus_state mbus_state;
-
-/*
- * functions
- */
-unsigned int mvebu_sdram_bar(enum memory_bank bank);
-unsigned int mvebu_sdram_bs(enum memory_bank bank);
-void mvebu_sdram_size_adjust(enum memory_bank bank);
-int mvebu_mbus_probe(struct mbus_win windows[], int count);
-
-/*
- * Highspeed SERDES PHY config init, ported from bin_hdr
- * to mainline U-Boot
- */
-int serdes_phy_config(void);
-
-/*
- * DDR3 init / training code ported from Marvell bin_hdr. Now
- * available in mainline U-Boot in:
- * drivers/ddr/mvebu/
- */
-int ddr3_init(void);
-#endif /* __ASSEMBLY__ */
-#endif /* _ARMADA_XP_CPU_H */
diff --git a/arch/arm/include/asm/arch-armada-xp/soc.h b/arch/arm/include/asm/arch-armada-xp/soc.h
deleted file mode 100644
index 963e7ac..0000000
--- a/arch/arm/include/asm/arch-armada-xp/soc.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * Header file for the Marvell's Feroceon CPU core.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _ASM_ARCH_ARMADA_XP_H
-#define _ASM_ARCH_ARMADA_XP_H
-
-#define SOC_MV78460_ID		0x7846
-
-/* TCLK Core Clock definition */
-#ifndef CONFIG_SYS_TCLK
-#define CONFIG_SYS_TCLK		250000000	/* 250MHz */
-#endif
-
-/* SOC specific definations */
-#define INTREG_BASE		0xd0000000
-#define INTREG_BASE_ADDR_REG	(INTREG_BASE + 0x20080)
-#define SOC_REGS_PHY_BASE	0xf1000000
-#define MVEBU_REGISTER(x)	(SOC_REGS_PHY_BASE + x)
-
-#define MVEBU_SDRAM_SCRATCH	(MVEBU_REGISTER(0x01504))
-#define MVEBU_SPI_BASE		(MVEBU_REGISTER(0x10600))
-#define MVEBU_TWSI_BASE		(MVEBU_REGISTER(0x11000))
-#define MVEBU_UART0_BASE	(MVEBU_REGISTER(0x12000))
-#define MVEBU_UART1_BASE	(MVEBU_REGISTER(0x12100))
-#define MVEBU_MPP_BASE		(MVEBU_REGISTER(0x18000))
-#define MVEBU_GPIO0_BASE	(MVEBU_REGISTER(0x18100))
-#define MVEBU_GPIO1_BASE	(MVEBU_REGISTER(0x18140))
-#define MVEBU_GPIO2_BASE	(MVEBU_REGISTER(0x18180))
-#define MVEBU_SYSTEM_REG_BASE	(MVEBU_REGISTER(0x18200))
-#define MVEBU_CPU_WIN_BASE	(MVEBU_REGISTER(0x20000))
-#define MVEBU_SDRAM_BASE	(MVEBU_REGISTER(0x20180))
-#define MVEBU_TIMER_BASE	(MVEBU_REGISTER(0x20300))
-#define MVEBU_EGIGA2_BASE	(MVEBU_REGISTER(0x30000))
-#define MVEBU_EGIGA3_BASE	(MVEBU_REGISTER(0x34000))
-#define MVEBU_REG_PCIE_BASE	(MVEBU_REGISTER(0x40000))
-#define MVEBU_EGIGA0_BASE	(MVEBU_REGISTER(0x70000))
-#define MVEBU_EGIGA1_BASE	(MVEBU_REGISTER(0x74000))
-
-#define SDRAM_MAX_CS		4
-#define SDRAM_ADDR_MASK		0xFF000000
-
-/* Armada XP GbE controller has 4 ports */
-#define MAX_MVNETA_DEVS		4
-
-/* Kirkwood CPU memory windows */
-#define MVCPU_WIN_CTRL_DATA	CPU_WIN_CTRL_DATA
-#define MVCPU_WIN_ENABLE	CPU_WIN_ENABLE
-#define MVCPU_WIN_DISABLE	CPU_WIN_DISABLE
-
-#endif /* _ASM_ARCH_ARMADA_XP_H */