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| author | Adrian Alonso <aalonso@freescale.com> | 2015-08-11 11:19:50 -0500 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2015-09-02 15:31:33 +0200 |
| commit | 03f0e4c7cd316a4b0b68776e39865ccf60a883a6 (patch) | |
| tree | 51dee43500d79a4ceb5d3c5b9814b942629b00fc /arch/arm/include/asm/imx-common/iomux-v3.h | |
| parent | 48469c2d88864ff94cb37e1c2f9a22ac0cd5d47f (diff) | |
| download | u-boot-imx-03f0e4c7cd316a4b0b68776e39865ccf60a883a6.zip u-boot-imx-03f0e4c7cd316a4b0b68776e39865ccf60a883a6.tar.gz u-boot-imx-03f0e4c7cd316a4b0b68776e39865ccf60a883a6.tar.bz2 | |
imx: iomux-v3: add imx7d support for iomuxc
* Add imx7d support for iomux controller
* imx7d has two iomux controllers iomuxc (0x3033000) and iomuxc-lpsr
(0x302C0000) each conroller provides control and mux mode pad
registers but shares iomuxc input select register with iomuxc-lpsr
IOMUX_CONFIG_LPSR flag is used to properly set daisy chain settings
for iomuxc-lpsr pads.
* Since mx7d introduces LPSR IOMUX pins, add new base to IOMUX v3
driver for these LPSR pins.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Diffstat (limited to 'arch/arm/include/asm/imx-common/iomux-v3.h')
| -rw-r--r-- | arch/arm/include/asm/imx-common/iomux-v3.h | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index 42098a3..1a80a96 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -85,6 +85,36 @@ typedef u64 iomux_v3_cfg_t; #define NO_PAD_CTRL (1 << 17) +#ifdef CONFIG_MX7 + +#define IOMUX_LPSR_SEL_INPUT_OFS 0x70000 +#define IOMUX_CONFIG_LPSR 0x8 +#define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \ + MUX_MODE_SHIFT) + +#define PAD_CTL_DSE_1P8V_140OHM (0x0<<0) +#define PAD_CTL_DSE_1P8V_35OHM (0x1<<0) +#define PAD_CTL_DSE_1P8V_70OHM (0x2<<0) +#define PAD_CTL_DSE_1P8V_23OHM (0x3<<0) + +#define PAD_CTL_DSE_3P3V_196OHM (0x0<<0) +#define PAD_CTL_DSE_3P3V_49OHM (0x1<<0) +#define PAD_CTL_DSE_3P3V_98OHM (0x2<<0) +#define PAD_CTL_DSE_3P3V_32OHM (0x3<<0) + +#define PAD_CTL_SRE_FAST (0 << 2) +#define PAD_CTL_SRE_SLOW (0x1 << 2) + +#define PAD_CTL_HYS (0x1 << 3) +#define PAD_CTL_PUE (0x1 << 4) + +#define PAD_CTL_PUS_PD100KOHM ((0x0 << 5) | PAD_CTL_PUE) +#define PAD_CTL_PUS_PU5KOHM ((0x1 << 5) | PAD_CTL_PUE) +#define PAD_CTL_PUS_PU47KOHM ((0x2 << 5) | PAD_CTL_PUE) +#define PAD_CTL_PUS_PU100KOHM ((0x3 << 5) | PAD_CTL_PUE) + +#else + #ifdef CONFIG_MX6 #define PAD_CTL_HYS (1 << 16) @@ -173,6 +203,8 @@ typedef u64 iomux_v3_cfg_t; #define PAD_CTL_SRE_SLOW (0 << 0) #define PAD_CTL_SRE_FAST (1 << 0) +#endif + #define IOMUX_CONFIG_SION 0x10 #define GPIO_PIN_MASK 0x1f |