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authorAneesh V <aneesh@ti.com>2011-06-16 23:30:47 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2011-07-04 10:55:25 +0200
commit2c451f7831208741d0ff7ca6046cffcd9ee49def (patch)
treeec885d6ce9bc97eca3128e83e9af35c5b063ffe1 /arch/arm/include/asm/armv7.h
parent4c93da7c392737f2036130c240e2b4bea773d703 (diff)
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armv7: cache maintenance operations for armv7
- Add a framework for layered cache maintenance - separate out SOC specific outer cache maintenance from maintenance of caches known to CPU - Add generic ARMv7 cache maintenance operations that affect all caches known to ARMv7 CPUs. For instance in Cortex-A8 these opertions will affect both L1 and L2 caches. In Cortex-A9 these will affect only L1 cache - D-cache operations supported: - Invalidate entire D-cache - Invalidate D-cache range - Flush(clean & invalidate) entire D-cache - Flush D-cache range - I-cache operations supported: - Invalidate entire I-cache - Add maintenance functions for TLB, branch predictor array etc. - Enable -march=armv7-a so that armv7 assembly instructions can be used Signed-off-by: Aneesh V <aneesh@ti.com>
Diffstat (limited to 'arch/arm/include/asm/armv7.h')
-rw-r--r--arch/arm/include/asm/armv7.h67
1 files changed, 67 insertions, 0 deletions
diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
new file mode 100644
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--- /dev/null
+++ b/arch/arm/include/asm/armv7.h
@@ -0,0 +1,67 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef ARMV7_H
+#define ARMV7_H
+#include <linux/types.h>
+
+/* CCSIDR */
+#define CCSIDR_LINE_SIZE_OFFSET 0
+#define CCSIDR_LINE_SIZE_MASK 0x7
+#define CCSIDR_ASSOCIATIVITY_OFFSET 3
+#define CCSIDR_ASSOCIATIVITY_MASK (0x3FF << 3)
+#define CCSIDR_NUM_SETS_OFFSET 13
+#define CCSIDR_NUM_SETS_MASK (0x7FFF << 13)
+
+/*
+ * Values for InD field in CSSELR
+ * Selects the type of cache
+ */
+#define ARMV7_CSSELR_IND_DATA_UNIFIED 0
+#define ARMV7_CSSELR_IND_INSTRUCTION 1
+
+/* Values for Ctype fields in CLIDR */
+#define ARMV7_CLIDR_CTYPE_NO_CACHE 0
+#define ARMV7_CLIDR_CTYPE_INSTRUCTION_ONLY 1
+#define ARMV7_CLIDR_CTYPE_DATA_ONLY 2
+#define ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA 3
+#define ARMV7_CLIDR_CTYPE_UNIFIED 4
+
+/*
+ * CP15 Barrier instructions
+ * Please note that we have separate barrier instructions in ARMv7
+ * However, we use the CP15 based instructtions because we use
+ * -march=armv5 in U-Boot
+ */
+#define CP15ISB asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0))
+#define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0))
+#define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0))
+
+void v7_outer_cache_enable(void);
+void v7_outer_cache_disable(void);
+void v7_outer_cache_flush_all(void);
+void v7_outer_cache_inval_all(void);
+void v7_outer_cache_flush_range(u32 start, u32 end);
+void v7_outer_cache_inval_range(u32 start, u32 end);
+
+#endif