diff options
author | Soren Brinkmann <soren.brinkmann@xilinx.com> | 2013-11-21 13:38:54 -0800 |
---|---|---|
committer | Michal Simek <michal.simek@xilinx.com> | 2014-02-19 09:41:21 +0100 |
commit | 6c3e61de3c9e6fbc283c16269f2e86f8fe0e0a6c (patch) | |
tree | 273b1ac9fa49357cb26173fa286cbbdbc7add5d8 /arch/arm/include/asm/arch-zynq/clk.h | |
parent | 23d5c738664918b1cb11cfffe5fbd79940d68c49 (diff) | |
download | u-boot-imx-6c3e61de3c9e6fbc283c16269f2e86f8fe0e0a6c.zip u-boot-imx-6c3e61de3c9e6fbc283c16269f2e86f8fe0e0a6c.tar.gz u-boot-imx-6c3e61de3c9e6fbc283c16269f2e86f8fe0e0a6c.tar.bz2 |
zynq: Provide a framework to read clock frequencies
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm/include/asm/arch-zynq/clk.h')
-rw-r--r-- | arch/arm/include/asm/arch-zynq/clk.h | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-zynq/clk.h b/arch/arm/include/asm/arch-zynq/clk.h new file mode 100644 index 0000000..250c5bc --- /dev/null +++ b/arch/arm/include/asm/arch-zynq/clk.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2013 Xilinx Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ZYNQ_CLK_H_ +#define _ZYNQ_CLK_H_ + +enum zynq_clk { + armpll_clk, ddrpll_clk, iopll_clk, + cpu_6or4x_clk, cpu_3or2x_clk, cpu_2x_clk, cpu_1x_clk, + ddr2x_clk, ddr3x_clk, dci_clk, + lqspi_clk, smc_clk, pcap_clk, gem0_clk, gem1_clk, + fclk0_clk, fclk1_clk, fclk2_clk, fclk3_clk, can0_clk, can1_clk, + sdio0_clk, sdio1_clk, uart0_clk, uart1_clk, spi0_clk, spi1_clk, dma_clk, + usb0_aper_clk, usb1_aper_clk, gem0_aper_clk, gem1_aper_clk, + sdio0_aper_clk, sdio1_aper_clk, spi0_aper_clk, spi1_aper_clk, + can0_aper_clk, can1_aper_clk, i2c0_aper_clk, i2c1_aper_clk, + uart0_aper_clk, uart1_aper_clk, gpio_aper_clk, lqspi_aper_clk, + smc_aper_clk, swdt_clk, dbg_trc_clk, dbg_apb_clk, clk_max}; + +void zynq_clk_early_init(void); +int zynq_clk_set_rate(enum zynq_clk clk, unsigned long rate); +unsigned long zynq_clk_get_rate(enum zynq_clk clk); +const char *zynq_clk_get_name(enum zynq_clk clk); +unsigned long get_uart_clk(int dev_id); + +#endif |