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authorTom Warren <twarren@nvidia.com>2015-02-02 13:22:29 -0700
committerTom Warren <twarren@nvidia.com>2015-07-28 10:30:19 -0700
commit6c43f6c8d920caa1db01f5d0571a4d9ba720be15 (patch)
treeaa3cabc8a3354f298c2f0ec125094402d653fee3 /arch/arm/include/asm/arch-tegra210/clock.h
parent56079eccd18a65bd5eea2f6a665862932c61963c (diff)
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ARM: Tegra210: Add SoC code/include files for T210
All based off of Tegra124. As a Tegra210 board is brought up, these may change a bit to match the HW more closely, but probably 90% of this is identical to T124. Note that since T210 is a 64-bit build, it has no SPL component, and hence no cpu.c for Tegra210. Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/include/asm/arch-tegra210/clock.h')
-rw-r--r--arch/arm/include/asm/arch-tegra210/clock.h27
1 files changed, 27 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-tegra210/clock.h b/arch/arm/include/asm/arch-tegra210/clock.h
new file mode 100644
index 0000000..3501be2
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra210/clock.h
@@ -0,0 +1,27 @@
+/*
+ * (C) Copyright 2010-2015
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Tegra210 clock control definitions */
+
+#ifndef _TEGRA210_CLOCK_H_
+#define _TEGRA210_CLOCK_H_
+
+#include <asm/arch-tegra/clock.h>
+
+/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
+#define OSC_FREQ_SHIFT 28
+#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT)
+
+/* PLL bits that differ from generic clk_rst.h */
+#define PLLC_RESET 30
+#define PLLC_IDDQ 27
+#define PLLD_ENABLE_CLK 21
+#define PLLD_EN_LCKDET 28
+
+int tegra_plle_enable(void);
+
+#endif /* _TEGRA210_CLOCK_H_ */