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authorStephen Warren <swarren@nvidia.com>2015-02-24 14:08:29 -0700
committerTom Warren <twarren@nvidia.com>2015-03-04 10:09:01 -0700
commit790f7719e2635a3ff3f44473b060e01b5b5ebf74 (patch)
treea93d85ab77323e2d6536a324c3ee84c1ae2685ad /arch/arm/include/asm/arch-tegra20/pinmux.h
parentf2c60eed513ecc142e0a39373d5c16a14f976d6d (diff)
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ARM: tegra: pinmux: account for different drivegroup base registers
Tegra210 starts its drive group registers at a different offset from the APB MISC register block that other SoCs. Update the code to handle this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/include/asm/arch-tegra20/pinmux.h')
-rw-r--r--arch/arm/include/asm/arch-tegra20/pinmux.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-tegra20/pinmux.h b/arch/arm/include/asm/arch-tegra20/pinmux.h
index f7bc97f..bf35d50 100644
--- a/arch/arm/include/asm/arch-tegra20/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra20/pinmux.h
@@ -233,6 +233,7 @@ enum pmux_func {
PMUX_FUNC_COUNT,
};
+#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
#include <asm/arch-tegra/pinmux.h>
#endif /* _TEGRA20_PINMUX_H_ */