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| author | York Sun <yorksun@freescale.com> | 2015-01-06 13:18:49 -0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-02-24 13:09:14 -0800 |
| commit | b87e6f88e9218da3de371bb6cc8a34924153178e (patch) | |
| tree | fe1c672d5af630646b8c1193b9f00c2132e857f8 /arch/arm/include/asm/arch-tegra/uart.h | |
| parent | 49fd1f3f265efc00d61effa995bd6a733bf273d8 (diff) | |
| download | u-boot-imx-b87e6f88e9218da3de371bb6cc8a34924153178e.zip u-boot-imx-b87e6f88e9218da3de371bb6cc8a34924153178e.tar.gz u-boot-imx-b87e6f88e9218da3de371bb6cc8a34924153178e.tar.bz2 | |
armv8/fsl-lsch3: Add support for second DDR clock
FSL-LSCH3 platforms can have multiple DDR clocks. LS2085A has one clock for
general DDR controlers, and another clock for DP-DDR. DDR driver needs to
change to support multiple clocks.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/arm/include/asm/arch-tegra/uart.h')
0 files changed, 0 insertions, 0 deletions