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author | Tom Warren <twarren@nvidia.com> | 2015-06-25 09:50:44 -0700 |
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committer | Tom Warren <twarren@nvidia.com> | 2015-08-05 15:22:51 -0700 |
commit | 722e000ccd7226c5cd071590b5361620eb0b126c (patch) | |
tree | 257ddcaf4039dd6722e743e8a1f4035c2f85387f /arch/arm/include/asm/arch-tegra/clock.h | |
parent | 3e8650c0f9cc7fb29bd75c11d0173768fcc80203 (diff) | |
download | u-boot-imx-722e000ccd7226c5cd071590b5361620eb0b126c.zip u-boot-imx-722e000ccd7226c5cd071590b5361620eb0b126c.tar.gz u-boot-imx-722e000ccd7226c5cd071590b5361620eb0b126c.tar.bz2 |
Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc.
Added PLL variables (dividers mask/shift, lock enable/detect, etc.)
to new pllinfo struct for each Soc/PLL. PLLA/C/D/E/M/P/U/X.
Used pllinfo struct in all clock functions, validated on T210.
Should be equivalent to prior code on T124/114/30/20. Thanks
to Marcel Ziswiler for corrections to the T20/T30 values.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/include/asm/arch-tegra/clock.h')
-rw-r--r-- | arch/arm/include/asm/arch-tegra/clock.h | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h index 2274b14..d570d7f 100644 --- a/arch/arm/include/asm/arch-tegra/clock.h +++ b/arch/arm/include/asm/arch-tegra/clock.h @@ -338,6 +338,27 @@ void arch_timer_init(void); void tegra30_set_up_pllp(void); +/* Number of PLL-based clocks (i.e. not OSC or 32KHz) */ +#define CLOCK_ID_PLL_COUNT (CLOCK_ID_COUNT - 2) + +struct clk_pll_info { + u32 m_shift:5; /* DIVM_SHIFT */ + u32 n_shift:5; /* DIVN_SHIFT */ + u32 p_shift:5; /* DIVP_SHIFT */ + u32 kcp_shift:5; /* KCP/cpcon SHIFT */ + u32 kvco_shift:5; /* KVCO/lfcon SHIFT */ + u32 lock_ena:6; /* LOCK_ENABLE/EN_LOCKDET shift */ + u32 rsvd:1; + u32 m_mask:10; /* DIVM_MASK */ + u32 n_mask:12; /* DIVN_MASK */ + u32 p_mask:10; /* DIVP_MASK or VCO_MASK */ + u32 kcp_mask:10; /* KCP/CPCON MASK */ + u32 kvco_mask:10; /* KVCO/LFCON MASK */ + u32 lock_det:6; /* LOCK_DETECT/LOCKED shift */ + u32 rsvd2:6; +}; +extern struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT]; + /** * Enable output clock for external peripherals * |