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| author | Hans de Goede <hdegoede@redhat.com> | 2015-05-14 18:52:54 +0200 |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2015-05-19 18:46:44 +0200 |
| commit | 83edb2ace6f00dfbe2da1ec28964874a06997862 (patch) | |
| tree | 2be464e13b277f68a05fffd1aa7898038e20fea2 /arch/arm/include/asm/arch-sunxi | |
| parent | 8975cdf4bce6e562ebb5451a2d1a9beca096660b (diff) | |
| download | u-boot-imx-83edb2ace6f00dfbe2da1ec28964874a06997862.zip u-boot-imx-83edb2ace6f00dfbe2da1ec28964874a06997862.tar.gz u-boot-imx-83edb2ace6f00dfbe2da1ec28964874a06997862.tar.bz2 | |
sunxi: video: Fix lvds panel support for sun6i+
We've never tested the lvds panel support on sun6i+ SoCs until now, and
unsurprisingly the lvds code needed some fixes to work on my ga10h A33
tablet with lvds panel. This makes the panel on that tablet actually work.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Diffstat (limited to 'arch/arm/include/asm/arch-sunxi')
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 3 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/display.h | 12 |
2 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index bacd70a..6465f21 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -331,6 +331,9 @@ struct sunxi_ccm_reg { #define AHB_RESET_OFFSET_LCD1 5 #define AHB_RESET_OFFSET_LCD0 4 +/* ahb_reset2 offsets */ +#define AHB_RESET_OFFSET_LVDS 0 + /* apb2 reset */ #define APB2_RESET_UART_SHIFT (16) #define APB2_RESET_UART_MASK (0xff << APB2_RESET_UART_SHIFT) diff --git a/arch/arm/include/asm/arch-sunxi/display.h b/arch/arm/include/asm/arch-sunxi/display.h index 5e94253..ae95417 100644 --- a/arch/arm/include/asm/arch-sunxi/display.h +++ b/arch/arm/include/asm/arch-sunxi/display.h @@ -363,6 +363,11 @@ struct sunxi_tve_reg { #define SUNXI_LCDC_TCON0_TIMING_H_TOTAL(n) (((n) - 1) << 16) #define SUNXI_LCDC_TCON0_TIMING_V_BP(n) (((n) - 1) << 0) #define SUNXI_LCDC_TCON0_TIMING_V_TOTAL(n) (((n) * 2) << 16) +#ifdef CONFIG_SUNXI_GEN_SUN6I +#define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0 (1 << 20) +#else +#define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0 0 /* NA */ +#endif #define SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(n) ((n) << 26) #define SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE (1 << 31) #define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(x) ((x) << 28) @@ -372,8 +377,15 @@ struct sunxi_tve_reg { #define SUNXI_LCDC_TCON1_TIMING_H_TOTAL(n) (((n) - 1) << 16) #define SUNXI_LCDC_TCON1_TIMING_V_BP(n) (((n) - 1) << 0) #define SUNXI_LCDC_TCON1_TIMING_V_TOTAL(n) (((n) * 2) << 16) +#ifdef CONFIG_SUNXI_GEN_SUN6I +#define SUNXI_LCDC_LVDS_ANA0 0x40040320 +#define SUNXI_LCDC_LVDS_ANA0_EN_MB (1 << 31) +#define SUNXI_LCDC_LVDS_ANA0_DRVC (1 << 24) +#define SUNXI_LCDC_LVDS_ANA0_DRVD(x) ((x) << 20) +#else #define SUNXI_LCDC_LVDS_ANA0 0x3f310000 #define SUNXI_LCDC_LVDS_ANA0_UPDATE (1 << 22) +#endif #define SUNXI_LCDC_LVDS_ANA1_INIT1 (0x1f << 26 | 0x1f << 10) #define SUNXI_LCDC_LVDS_ANA1_INIT2 (0x1f << 16 | 0x1f << 00) |