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authorLokesh Vutla <lokeshvutla@ti.com>2012-05-22 00:03:27 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-07-07 14:07:24 +0200
commit7fd5b9bfe4a66a0eec232ab36ddafdd823e263c2 (patch)
tree053058219b842a5a69de87a6e931c1d4b9522152 /arch/arm/include/asm/arch-omap5/clocks.h
parent753bae8c5dd4ba92a39b06ea9a551be962053f93 (diff)
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OMAP5: Change voltages for omap5432
Change voltages for OMAP5432 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch/arm/include/asm/arch-omap5/clocks.h')
-rw-r--r--arch/arm/include/asm/arch-omap5/clocks.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h
index 409e0e3..5f1a7aa 100644
--- a/arch/arm/include/asm/arch-omap5/clocks.h
+++ b/arch/arm/include/asm/arch-omap5/clocks.h
@@ -480,6 +480,13 @@ struct omap5_prcm_regs {
u32 pad217[4];
u32 prm_vc_cfg_i2c_mode; /* 4ae07bb4 */
u32 prm_vc_cfg_i2c_clk; /* 4ae07bb8 */
+ u32 pad218[2];
+ u32 prm_sldo_core_setup; /* 4ae07bc4 */
+ u32 prm_sldo_core_ctrl; /* 4ae07bc8 */
+ u32 prm_sldo_mpu_setup; /* 4ae07bcc */
+ u32 prm_sldo_mpu_ctrl; /* 4ae07bd0 */
+ u32 prm_sldo_mm_setup; /* 4ae07bd4 */
+ u32 prm_sldo_mm_ctrl; /* 4ae07bd8 */
};
/* DPLL register offsets */
@@ -646,6 +653,9 @@ struct omap5_prcm_regs {
#define VDD_MPU 1000
#define VDD_MM 1000
#define VDD_CORE 1040
+#define VDD_MPU_5432 1150
+#define VDD_MM_5432 1150
+#define VDD_CORE_5432 1150
/* Standard offset is 0.5v expressed in uv */
#define PALMAS_SMPS_BASE_VOLT_UV 500000