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author | Peng Fan <Peng.Fan@freescale.com> | 2015-10-29 15:54:44 +0800 |
---|---|---|
committer | Stefano Babic <sbabic@denx.de> | 2015-11-12 17:38:09 +0100 |
commit | 8702f5ab5da686d0bb25c0dfbf1fc46bcf402a80 (patch) | |
tree | 87ea56a9f9eeda80a81ec64e4fa730531be1bcac /arch/arm/include/asm/arch-mx7/imx-regs.h | |
parent | 04acd0e5d9ace923dec8eed00ed5878cf462be70 (diff) | |
download | u-boot-imx-8702f5ab5da686d0bb25c0dfbf1fc46bcf402a80.zip u-boot-imx-8702f5ab5da686d0bb25c0dfbf1fc46bcf402a80.tar.gz u-boot-imx-8702f5ab5da686d0bb25c0dfbf1fc46bcf402a80.tar.bz2 |
imx: lcdif: use one register structure for i.MXes
Share one lcdif structure for i.MXes.
1. Discard struct mxs_lcdif_regs from imx-regs.h of i.MX7
2. Add i.MX6SX/6UL/7D support in imx-lcdif.h of imx-common
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'arch/arm/include/asm/arch-mx7/imx-regs.h')
-rw-r--r-- | arch/arm/include/asm/arch-mx7/imx-regs.h | 96 |
1 files changed, 1 insertions, 95 deletions
diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h index 9213374..e28a807 100644 --- a/arch/arm/include/asm/arch-mx7/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7/imx-regs.h @@ -217,6 +217,7 @@ #define SNVS_LPGPR 0x68 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include <asm/imx-common/regs-lcdif.h> #include <asm/types.h> extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); @@ -1032,101 +1033,6 @@ struct rdc_sema_regs { u16 rstgt; /* Reset Gate */ }; -/* eLCDIF controller registers */ -struct mxs_lcdif_regs { - u32 hw_lcdif_ctrl; /* 0x00 */ - u32 hw_lcdif_ctrl_set; - u32 hw_lcdif_ctrl_clr; - u32 hw_lcdif_ctrl_tog; - u32 hw_lcdif_ctrl1; /* 0x10 */ - u32 hw_lcdif_ctrl1_set; - u32 hw_lcdif_ctrl1_clr; - u32 hw_lcdif_ctrl1_tog; - u32 hw_lcdif_ctrl2; /* 0x20 */ - u32 hw_lcdif_ctrl2_set; - u32 hw_lcdif_ctrl2_clr; - u32 hw_lcdif_ctrl2_tog; - u32 hw_lcdif_transfer_count; /* 0x30 */ - u32 reserved1[3]; - u32 hw_lcdif_cur_buf; /* 0x40 */ - u32 reserved2[3]; - u32 hw_lcdif_next_buf; /* 0x50 */ - u32 reserved3[3]; - u32 hw_lcdif_timing; /* 0x60 */ - u32 reserved4[3]; - u32 hw_lcdif_vdctrl0; /* 0x70 */ - u32 hw_lcdif_vdctrl0_set; - u32 hw_lcdif_vdctrl0_clr; - u32 hw_lcdif_vdctrl0_tog; - u32 hw_lcdif_vdctrl1; /* 0x80 */ - u32 reserved5[3]; - u32 hw_lcdif_vdctrl2; /* 0x90 */ - u32 reserved6[3]; - u32 hw_lcdif_vdctrl3; /* 0xa0 */ - u32 reserved7[3]; - u32 hw_lcdif_vdctrl4; /* 0xb0 */ - u32 reserved8[3]; - u32 hw_lcdif_dvictrl0; /* 0xc0 */ - u32 reserved9[3]; - u32 hw_lcdif_dvictrl1; /* 0xd0 */ - u32 reserved10[3]; - u32 hw_lcdif_dvictrl2; /* 0xe0 */ - u32 reserved11[3]; - u32 hw_lcdif_dvictrl3; /* 0xf0 */ - u32 reserved12[3]; - u32 hw_lcdif_dvictrl4; /* 0x100 */ - u32 reserved13[3]; - u32 hw_lcdif_csc_coeffctrl0; /* 0x110 */ - u32 reserved14[3]; - u32 hw_lcdif_csc_coeffctrl1; /* 0x120 */ - u32 reserved15[3]; - u32 hw_lcdif_csc_coeffctrl2; /* 0x130 */ - u32 reserved16[3]; - u32 hw_lcdif_csc_coeffctrl3; /* 0x140 */ - u32 reserved17[3]; - u32 hw_lcdif_csc_coeffctrl4; /* 0x150 */ - u32 reserved18[3]; - u32 hw_lcdif_csc_offset; /* 0x160 */ - u32 reserved19[3]; - u32 hw_lcdif_csc_limit; /* 0x170 */ - u32 reserved20[3]; - u32 hw_lcdif_data; /* 0x180 */ - u32 reserved21[3]; - u32 hw_lcdif_bm_error_stat; /* 0x190 */ - u32 reserved22[3]; - u32 hw_lcdif_crc_stat; /* 0x1a0 */ - u32 reserved23[3]; - u32 hw_lcdif_lcdif_stat; /* 0x1b0 */ - u32 reserved24[3]; - u32 hw_lcdif_version; /* 0x1c0 */ - u32 reserved25[3]; - u32 hw_lcdif_debug0; /* 0x1d0 */ - u32 reserved26[3]; - u32 hw_lcdif_debug1; /* 0x1e0 */ - u32 reserved27[3]; - u32 hw_lcdif_debug2; /* 0x1f0 */ - u32 reserved28[3]; - u32 hw_lcdif_thres; /* 0x200 */ - u32 reserved29[3]; - u32 hw_lcdif_as_ctrl; /* 0x210 */ - u32 reserved30[3]; - u32 hw_lcdif_as_buf; /* 0x220 */ - u32 reserved31[3]; - u32 hw_lcdif_as_next_buf; /* 0x230 */ - u32 reserved32[3]; - u32 hw_lcdif_as_clrkeylow; /* 0x240 */ - u32 reserved33[3]; - u32 hw_lcdif_as_clrkeyhigh; /* 0x250 */ - u32 reserved34[3]; - u32 hw_lcdif_as_sync_delay; /* 0x260 */ - u32 reserved35[3]; - u32 hw_lcdif_as_debug3; /* 0x270 */ - u32 reserved36[3]; - u32 hw_lcdif_as_debug4; /* 0x280 */ - u32 reserved37[3]; - u32 hw_lcdif_as_debug5; /* 0x290 */ -}; - #define MXS_LCDIF_BASE ELCDIF1_IPS_BASE_ADDR #define LCDIF_CTRL_SFTRST (1 << 31) |