ENGR00315894-54 iMX6SX/SL: Modify SOC to support two ENET

iMX6SX has different enet system clocks with iMX6SL, and has two ENET
controllers. So update clocks and soc APIs accordingly to support this
features.

1. Modify the clock API "enable_enet_clock" to enable enet system clock
   for enet controllers.
2. Enet RGMII TX clock source may come from external or internal PLL.
   By default, use the external phy CLK_25M output as TX clock source.
   When using internal PLL as source, the function enable_fec_anatop_clock
   must be called to enable clock for each enet controller.
3. Modify the MAC address function "imx_get_mac_from_fuse" to get either
   ENET MAC address.
4. Add configuration "CONFIG_FEC_MXC_25M_REF_CLK" to enable ENET 25Mhz
   reference clock.
5. Modify imx6slevk BSP to fit the new APIs.

Signed-off-by: Fugang Duan  <B38611@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>

1 files changed, 17 insertions, 0 deletions

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 39df1fd..30b750e 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -591,6 +591,22 @@ struct fuse_bank1_regs {
 	u32     ana2;
 };
 
+#ifdef CONFIG_MX6SX
+struct fuse_bank4_regs {
+	u32 sjc_resp_low;
+	u32 rsvd0[3];
+	u32 sjc_resp_high;
+	u32 rsvd1[3];
+	u32 mac_addr0;
+	u32 rsvd2[3];
+	u32 mac_addr1;
+	u32 rsvd3[3];
+	u32 mac_addr2;
+	u32 rsvd4[7];
+	u32 gp1;
+	u32 rsvd5[7];
+};
+#else
 struct fuse_bank4_regs {
 	u32	sjc_resp_low;
 	u32     rsvd0[3];
@@ -605,6 +621,7 @@ struct fuse_bank4_regs {
 	u32	gp2;
 	u32	rsvd5[3];
 };
+#endif
 
 struct aipstz_regs {
 	u32	mprot0;