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| author | Wolfgang Denk <wd@denx.de> | 2010-10-20 00:10:07 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2010-10-20 00:10:07 +0200 |
| commit | b18815752f3d6db27877606e4e069e3f6cfe3a19 (patch) | |
| tree | 6c020a953e33ff48304d94f3ec586431321cd147 /arch/arm/include/asm/arch-mx5/asm-offsets.h | |
| parent | 683e9f1ea5586d7538c9afa397a0a86ccfb21bff (diff) | |
| parent | 2ea88b063e1547ff013b00e74a4656603be5ed5f (diff) | |
| download | u-boot-imx-b18815752f3d6db27877606e4e069e3f6cfe3a19.zip u-boot-imx-b18815752f3d6db27877606e4e069e3f6cfe3a19.tar.gz u-boot-imx-b18815752f3d6db27877606e4e069e3f6cfe3a19.tar.bz2 | |
Merge branch 'master' of git://git.denx.de/u-boot-arm
Diffstat (limited to 'arch/arm/include/asm/arch-mx5/asm-offsets.h')
| -rw-r--r-- | arch/arm/include/asm/arch-mx5/asm-offsets.h | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-mx5/asm-offsets.h b/arch/arm/include/asm/arch-mx5/asm-offsets.h new file mode 100644 index 0000000..afd2728 --- /dev/null +++ b/arch/arm/include/asm/arch-mx5/asm-offsets.h @@ -0,0 +1,50 @@ +/* + * needed for arch/arm/cpu/armv7/mx51/lowlevel_init.S + * + * These should be auto-generated + */ +/* CCM */ +#define CLKCTL_CCR 0x00 +#define CLKCTL_CCDR 0x04 +#define CLKCTL_CSR 0x08 +#define CLKCTL_CCSR 0x0C +#define CLKCTL_CACRR 0x10 +#define CLKCTL_CBCDR 0x14 +#define CLKCTL_CBCMR 0x18 +#define CLKCTL_CSCMR1 0x1C +#define CLKCTL_CSCMR2 0x20 +#define CLKCTL_CSCDR1 0x24 +#define CLKCTL_CS1CDR 0x28 +#define CLKCTL_CS2CDR 0x2C +#define CLKCTL_CDCDR 0x30 +#define CLKCTL_CHSCCDR 0x34 +#define CLKCTL_CSCDR2 0x38 +#define CLKCTL_CSCDR3 0x3C +#define CLKCTL_CSCDR4 0x40 +#define CLKCTL_CWDR 0x44 +#define CLKCTL_CDHIPR 0x48 +#define CLKCTL_CDCR 0x4C +#define CLKCTL_CTOR 0x50 +#define CLKCTL_CLPCR 0x54 +#define CLKCTL_CISR 0x58 +#define CLKCTL_CIMR 0x5C +#define CLKCTL_CCOSR 0x60 +#define CLKCTL_CGPR 0x64 +#define CLKCTL_CCGR0 0x68 +#define CLKCTL_CCGR1 0x6C +#define CLKCTL_CCGR2 0x70 +#define CLKCTL_CCGR3 0x74 +#define CLKCTL_CCGR4 0x78 +#define CLKCTL_CCGR5 0x7C +#define CLKCTL_CCGR6 0x80 +#define CLKCTL_CMEOR 0x84 + +/* DPLL */ +#define PLL_DP_CTL 0x00 +#define PLL_DP_CONFIG 0x04 +#define PLL_DP_OP 0x08 +#define PLL_DP_MFD 0x0C +#define PLL_DP_MFN 0x10 +#define PLL_DP_HFS_OP 0x1C +#define PLL_DP_HFS_MFD 0x20 +#define PLL_DP_HFS_MFN 0x24 |