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| author | Eric Nelson <eric.nelson@boundarydevices.com> | 2012-01-31 07:52:03 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-02-27 21:19:23 +0100 |
| commit | 08c61a589b75154e274394972acffe71dbdb75c1 (patch) | |
| tree | e170008e780d12ab3d8f37a4892d6211efb59c9f /arch/arm/include/asm/arch-mx31/imx-regs.h | |
| parent | 4b3a30e9ae304f1350d7dc17b3e0d2ef90e2b668 (diff) | |
| download | u-boot-imx-08c61a589b75154e274394972acffe71dbdb75c1.zip u-boot-imx-08c61a589b75154e274394972acffe71dbdb75c1.tar.gz u-boot-imx-08c61a589b75154e274394972acffe71dbdb75c1.tar.bz2 | |
mxc_spi: move machine specifics into CPU headers
Move (E)CSPI register declarations into the imx-regs.h files for each supported CPU
Introduce two new macros to control conditional setup
MXC_CSPI - Used for processors with the Configurable Serial Peripheral Interface (MX3x)
MXC_ECSPI - For processors with Enhanced Configurable... (MX5x, MX6x)
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Jason Liu <jason.hui@linaro.org>
Tested-by: Jason Liu <jason.hui@linaro.org>
Diffstat (limited to 'arch/arm/include/asm/arch-mx31/imx-regs.h')
| -rw-r--r-- | arch/arm/include/asm/arch-mx31/imx-regs.h | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index 798cc74..6454acb 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -901,4 +901,31 @@ struct esdc_regs { #define MXC_EHCI_IPPUE_DOWN (1 << 8) #define MXC_EHCI_IPPUE_UP (1 << 9) +/* + * CSPI register definitions + */ +#define MXC_CSPI +#define MXC_CSPICTRL_EN (1 << 0) +#define MXC_CSPICTRL_MODE (1 << 1) +#define MXC_CSPICTRL_XCH (1 << 2) +#define MXC_CSPICTRL_SMC (1 << 3) +#define MXC_CSPICTRL_POL (1 << 4) +#define MXC_CSPICTRL_PHA (1 << 5) +#define MXC_CSPICTRL_SSCTL (1 << 6) +#define MXC_CSPICTRL_SSPOL (1 << 7) +#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24) +#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8) +#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16) +#define MXC_CSPICTRL_TC (1 << 8) +#define MXC_CSPICTRL_RXOVF (1 << 6) +#define MXC_CSPICTRL_MAXBITS 0x1f + +#define MXC_CSPIPERIOD_32KHZ (1 << 15) +#define MAX_SPI_BYTES 4 + +#define MXC_SPI_BASE_ADDRESSES \ + 0x43fa4000, \ + 0x50010000, \ + 0x53f84000, + #endif /* __ASM_ARCH_MX31_IMX_REGS_H */ |