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| author | Alison Wang <b18965@freescale.com> | 2015-03-12 11:31:44 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-04-21 10:19:19 -0700 |
| commit | 036f3f3379d56a4eb64d5154b47a8981a478fe3e (patch) | |
| tree | aeea3c64015236dca6ed8a7ab3b74b9f61e1962d /arch/arm/include/asm/arch-ls102xa | |
| parent | d77447fdb122dab290fb1ad184a62456011e6e06 (diff) | |
| download | u-boot-imx-036f3f3379d56a4eb64d5154b47a8981a478fe3e.zip u-boot-imx-036f3f3379d56a4eb64d5154b47a8981a478fe3e.tar.gz u-boot-imx-036f3f3379d56a4eb64d5154b47a8981a478fe3e.tar.bz2 | |
arm/ls102xa:Add support of conditional workaround implementation as per SoC ver
For LS102xA, some workarounds are only used in VER1.0, so silicon
version detection are added for QDS and TWR boards.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/arm/include/asm/arch-ls102xa')
| -rw-r--r-- | arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 3a64afc..a8122c1 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -17,6 +17,9 @@ #define SOC_VER_LS1021 0x11 #define SOC_VER_LS1022 0x12 +#define SOC_MAJOR_VER_1_0 0x1 +#define SOC_MAJOR_VER_2_0 0x2 + #define CCSR_BRR_OFFSET 0xe4 #define CCSR_SCRATCHRW1_OFFSET 0x200 |