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authorWang Huan <b18965@freescale.com>2014-09-05 13:52:34 +0800
committerYork Sun <yorksun@freescale.com>2014-09-08 10:30:32 -0700
commitd60a2099a20254b33a314895a4b5e6a21aebd135 (patch)
tree2fb79855edd6466a89c84cc4ce6210802aa75d06 /arch/arm/include/asm/arch-ls102xa/clock.h
parentd6c1ffc7d23f4fe4ae8c91101861055b8e1501b6 (diff)
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arm: ls102xa: Add Freescale LS102xA SoC support
The QorIQ LS1 family is built on Layerscape architecture, the industry's first software-aware, core-agnostic networking architecture to offer unprecedented efficiency and scale. Freescale LS102xA is a set of SoCs combines two ARM Cortex-A7 cores that have been optimized for high reliability and pack the highest level of integration available for sub-3 W embedded communications processors with Layerscape architecture and with a comprehensive enablement model focused on ease of programmability. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Jason Jin <jason.jin@freescale.com> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Diffstat (limited to 'arch/arm/include/asm/arch-ls102xa/clock.h')
-rw-r--r--arch/arm/include/asm/arch-ls102xa/clock.h23
1 files changed, 23 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-ls102xa/clock.h b/arch/arm/include/asm/arch-ls102xa/clock.h
new file mode 100644
index 0000000..fd36bb0
--- /dev/null
+++ b/arch/arm/include/asm/arch-ls102xa/clock.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#ifndef __ASM_ARCH_LS102XA_CLOCK_H_
+#define __ASM_ARCH_LS102XA_CLOCK_H_
+
+#include <common.h>
+
+enum mxc_clock {
+ MXC_ARM_CLK = 0,
+ MXC_UART_CLK,
+ MXC_ESDHC_CLK,
+ MXC_I2C_CLK,
+ MXC_DSPI_CLK,
+};
+
+unsigned int mxc_get_clock(enum mxc_clock clk);
+
+#endif /* __ASM_ARCH_LS102XA_CLOCK_H_ */