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| author | Priyanka Jain <priyanka.jain@nxp.com> | 2016-11-17 12:29:52 +0530 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-11-22 11:37:31 -0800 |
| commit | f6b96ff665844291a76de139bfbaa75fc0c7d917 (patch) | |
| tree | 7a111f676696d9d5c39f85f2df3cf2b2f145ba46 /arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | |
| parent | f6a70b3a92d07cf99d83c57fd9856312d8ab2807 (diff) | |
| download | u-boot-imx-f6b96ff665844291a76de139bfbaa75fc0c7d917.zip u-boot-imx-f6b96ff665844291a76de139bfbaa75fc0c7d917.tar.gz u-boot-imx-f6b96ff665844291a76de139bfbaa75fc0c7d917.tar.bz2 | |
armv8: lsch3: Use SVR based timer base address detection
Timer controller base address has been changed from
LS2080A SoC (and its personalities) to new SoCs like
LS2088A, LS1088A.
Use SVR based timer base address detection to avoid compile time #ifdef.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h')
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 09c1033..2df56f7 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -23,7 +23,8 @@ #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000) #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600) -#define CONFIG_SYS_FSL_TIMER_ADDR 0x023d0000 +#define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR 0x023d0000 +#define CONFIG_SYS_FSL_TIMER_ADDR 0x023e0000 #define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \ 0x18A0) #define FSL_PMU_PCTBENR_OFFSET (CONFIG_SYS_FSL_PMU_ADDR + 0x8A0) |