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| author | Alex Porosanu <alexandru.porosanu@freescale.com> | 2016-04-29 15:17:58 +0300 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-05-18 08:51:46 -0700 |
| commit | e99d7193593cf6331ea04cd394a9a4cf18886ef0 (patch) | |
| tree | a187ad9403f8e304c9dd954aec3a8aad51557e08 /arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | |
| parent | 56747bfdbd6f2c5bc391d0c9d5eb20a6a2d50505 (diff) | |
| download | u-boot-imx-e99d7193593cf6331ea04cd394a9a4cf18886ef0.zip u-boot-imx-e99d7193593cf6331ea04cd394a9a4cf18886ef0.tar.gz u-boot-imx-e99d7193593cf6331ea04cd394a9a4cf18886ef0.tar.bz2 | |
arch/arm: add SEC JR0 offset
Freescale PPC SoCs do not hard-code security engine's Job Ring 0
address, rather a define is used. This patch adds the same
functionality to the ARM based SoCs (i.e. LS1/LS2 and i.MX parts)
Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h')
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 0bad0c7..57b99d4 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -37,8 +37,6 @@ #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) -#define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000) -#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000) #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000) #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200) @@ -157,6 +155,13 @@ struct sys_info { #define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET) +#define CONFIG_SYS_FSL_SEC_OFFSET 0x700000ull +#define CONFIG_SYS_FSL_JR0_OFFSET 0x710000ull +#define CONFIG_SYS_FSL_SEC_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) +#define CONFIG_SYS_FSL_JR0_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) + /* Device Configuration and Pin Control */ struct ccsr_gur { u32 porsr1; /* POR status 1 */ |