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| author | Mingkai Hu <mingkai.hu@nxp.com> | 2016-07-05 16:01:55 +0800 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-07-26 09:02:23 -0700 |
| commit | b528b9377df0e738c6904a639a1e78810936f825 (patch) | |
| tree | ab3f786883fc5988efad56848cdc65dff803e34f /arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h | |
| parent | da4d620c90eb6dd9466a89837ab8667048d856e3 (diff) | |
| download | u-boot-imx-b528b9377df0e738c6904a639a1e78810936f825.zip u-boot-imx-b528b9377df0e738c6904a639a1e78810936f825.tar.gz u-boot-imx-b528b9377df0e738c6904a639a1e78810936f825.tar.bz2 | |
armv8: fsl_lsch2: Add LS1046A SoC support
The LS1046A processor is built on the QorIQ LS series architecture
combining four ARM A72 processor cores with DPAA 1.0 support.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Mihai Bantea <mihai.bantea@freescale.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h')
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index 1f33404..e1b3f44 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -151,7 +151,7 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device); enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane); int is_serdes_prtcl_valid(int serdes, u32 prtcl); -#ifdef CONFIG_LS1043A +#ifdef CONFIG_FSL_LSCH2 const char *serdes_clock_to_string(u32 clock); int get_serdes_protocol(void); #endif |