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authorRajeshwari Birje <rajeshwari.s@samsung.com>2013-12-26 09:44:21 +0530
committerMinkyu Kang <mk7.kang@samsung.com>2013-12-30 16:50:34 +0900
commit060c227a2861b0702e34eabe08eea9cc5bb68b45 (patch)
tree8491031643b8226f1cb5a6f940f40e37dc8d67e8 /arch/arm/include/asm/arch-exynos/clk.h
parente89278c9331143f1c5f3bc97c90aee8bce76f8b4 (diff)
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Exynos5420: Add clock initialization for 5420
This patch adds code for clock initialization and clock settings of various IP's and controllers, required for Exynos5420 Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'arch/arm/include/asm/arch-exynos/clk.h')
-rw-r--r--arch/arm/include/asm/arch-exynos/clk.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h
index 1d6fa93..cdeef32 100644
--- a/arch/arm/include/asm/arch-exynos/clk.h
+++ b/arch/arm/include/asm/arch-exynos/clk.h
@@ -14,6 +14,7 @@
#define HPLL 3
#define VPLL 4
#define BPLL 5
+#define RPLL 6
enum pll_src_bit {
EXYNOS_SRC_MPLL = 6,