diff options
| author | Konstantin Porotchkin <kostap@marvell.com> | 2016-12-04 18:34:13 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2016-12-12 09:05:28 +0100 |
| commit | b58385df3a448ba90e4ed0b699d275597ff73ea9 (patch) | |
| tree | 273e1894345edac6a05a7208014248c8587bdbeb /arch/arm/include/asm/arch-armada8k | |
| parent | 81647eaff31a4f2e5a270a5c71da0941b5ed952a (diff) | |
| download | u-boot-imx-b58385df3a448ba90e4ed0b699d275597ff73ea9.zip u-boot-imx-b58385df3a448ba90e4ed0b699d275597ff73ea9.tar.gz u-boot-imx-b58385df3a448ba90e4ed0b699d275597ff73ea9.tar.bz2 | |
arm64: mvebu: Add L3 cache flush functionality to A8K family
Add missing L3 cache flush functionality which absence prevents
Linux kernel from normal boot in case the L3 cache is enabled
by ATF.
The L3 cache is named the "last level" cache in order to keep
the terminology similar to the ATF code.
This cache should not be disabled by u-boot since the Linux
kernel cannot activate it, so it is activates at ATF stage.
However the cache flush is required for preventing data corruption
after disabling the MMU and the data cache before passing control
to the loaded Linux image.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'arch/arm/include/asm/arch-armada8k')
| -rw-r--r-- | arch/arm/include/asm/arch-armada8k/cache_llc.h | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-armada8k/cache_llc.h b/arch/arm/include/asm/arch-armada8k/cache_llc.h new file mode 100644 index 0000000..8f97e6d --- /dev/null +++ b/arch/arm/include/asm/arch-armada8k/cache_llc.h @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2016 Marvell International Ltd. + * + * SPDX-License-Identifier: GPL-2.0 + * https://spdx.org/licenses + */ + +#ifndef _CACHE_LLC_H_ +#define _CACHE_LLC_H_ + +/* Armada-7K/8K last level cache */ + +#define MVEBU_A8K_REGS_BASE_MSB 0xf000 +#define LLC_BASE_ADDR 0x8000 +#define LLC_CACHE_SYNC 0x700 +#define LLC_CACHE_SYNC_COMPLETE 0x730 +#define LLC_FLUSH_BY_WAY 0x7fc +#define LLC_WAY_MASK 0xffffffff +#define LLC_CACHE_SYNC_MASK 0x1 + +#endif /* _CACHE_LLC_H_ */ |