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| author | Konstantin Porotchkin <kostap@marvell.com> | 2016-12-08 12:22:29 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2016-12-12 09:04:52 +0100 |
| commit | 656e6cc86b96be88f99f6f3ef1df3ef3122a8766 (patch) | |
| tree | 67447ddfcc3e33aae76d5a16f4c0f4d30830c472 /arch/arm/include/asm/arch-armada8k/soc-info.h | |
| parent | fa61ef6b4980dbc009e93baadbfcb1daa359d74b (diff) | |
| download | u-boot-imx-656e6cc86b96be88f99f6f3ef1df3ef3122a8766.zip u-boot-imx-656e6cc86b96be88f99f6f3ef1df3ef3122a8766.tar.gz u-boot-imx-656e6cc86b96be88f99f6f3ef1df3ef3122a8766.tar.bz2 | |
arm64: mvebu: pinctrl: Add pin control driver for A8K family
Add a DM port of Marvell pin control driver.
The A8K SoC family contains several silicone dies interconnected
in a single package. Every die is normally equipped with its own
pin controller unit.
There are 2 pin controllers in A70x0 SoC and 3 in A80x0 SoC.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'arch/arm/include/asm/arch-armada8k/soc-info.h')
| -rw-r--r-- | arch/arm/include/asm/arch-armada8k/soc-info.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-armada8k/soc-info.h b/arch/arm/include/asm/arch-armada8k/soc-info.h new file mode 100644 index 0000000..bae3995 --- /dev/null +++ b/arch/arm/include/asm/arch-armada8k/soc-info.h @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2016 Marvell International Ltd. + * + * SPDX-License-Identifier: GPL-2.0 + * https://spdx.org/licenses + */ + +#ifndef _SOC_INFO_H_ +#define _SOC_INFO_H_ + +/* Pin Ctrl driver definitions */ +#define BITS_PER_PIN 4 +#define PIN_FUNC_MASK ((1 << BITS_PER_PIN) - 1) +#define PIN_REG_SHIFT 3 +#define PIN_FIELD_MASK ((1 << PIN_REG_SHIFT) - 1) + +#endif /* _SOC_INFO_H_ */ |