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authorYe Li <ye.li@nxp.com>2016-05-03 14:24:33 +0800
committerYe Li <ye.li@nxp.com>2016-05-03 14:36:07 +0800
commit39ea1ae1f0d68871c070b7db3e67435069c21254 (patch)
tree60b371c48e65dc8f2d5324ba5b16d43e4695a857 /arch/arm/imx-common
parent0a4b78f3b376aaede9d693bcf8aba359390cab27 (diff)
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MLK-12737 mx6qp/mx6dp: Fix runtime CPU type checking issue
2016 u-boot added dummy CPU types for the i.MX6QP and i.MX6DP. When doing runtime cpu type checking, we can't use CPU type of i.MX6Q and i.MX6D for them more, which is ok in 2015 u-boot. This patch adds the MXC_CPU_MX6QP and MXC_CPU_MX6DP at some places missed to do the checking. Signed-off-by: Ye Li <ye.li@nxp.com>
Diffstat (limited to 'arch/arm/imx-common')
-rw-r--r--arch/arm/imx-common/hab.c18
-rw-r--r--arch/arm/imx-common/sata.c3
-rw-r--r--arch/arm/imx-common/timer.c3
3 files changed, 20 insertions, 4 deletions
diff --git a/arch/arm/imx-common/hab.c b/arch/arm/imx-common/hab.c
index bec3c59..1ff4bd9 100644
--- a/arch/arm/imx-common/hab.c
+++ b/arch/arm/imx-common/hab.c
@@ -17,6 +17,9 @@
#define hab_rvt_report_event_p \
( \
+ (is_cpu_type(MXC_CPU_MX6QP) || \
+ is_cpu_type(MXC_CPU_MX6DP)) ? \
+ ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \
((is_cpu_type(MXC_CPU_MX6Q) || \
is_cpu_type(MXC_CPU_MX6D)) && \
(soc_rev() >= CHIP_REV_1_5)) ? \
@@ -30,6 +33,9 @@
#define hab_rvt_report_status_p \
( \
+ (is_cpu_type(MXC_CPU_MX6QP) || \
+ is_cpu_type(MXC_CPU_MX6DP)) ? \
+ ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
((is_cpu_type(MXC_CPU_MX6Q) || \
is_cpu_type(MXC_CPU_MX6D)) && \
(soc_rev() >= CHIP_REV_1_5)) ? \
@@ -43,6 +49,9 @@
#define hab_rvt_authenticate_image_p \
( \
+ (is_cpu_type(MXC_CPU_MX6QP) || \
+ is_cpu_type(MXC_CPU_MX6DP)) ? \
+ ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
((is_cpu_type(MXC_CPU_MX6Q) || \
is_cpu_type(MXC_CPU_MX6D)) && \
(soc_rev() >= CHIP_REV_1_5)) ? \
@@ -56,6 +65,9 @@
#define hab_rvt_entry_p \
( \
+ (is_cpu_type(MXC_CPU_MX6QP) || \
+ is_cpu_type(MXC_CPU_MX6DP)) ? \
+ ((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \
((is_cpu_type(MXC_CPU_MX6Q) || \
is_cpu_type(MXC_CPU_MX6D)) && \
(soc_rev() >= CHIP_REV_1_5)) ? \
@@ -69,6 +81,9 @@
#define hab_rvt_exit_p \
( \
+ (is_cpu_type(MXC_CPU_MX6QP) || \
+ is_cpu_type(MXC_CPU_MX6DP)) ? \
+ ((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \
((is_cpu_type(MXC_CPU_MX6Q) || \
is_cpu_type(MXC_CPU_MX6D)) && \
(soc_rev() >= CHIP_REV_1_5)) ? \
@@ -437,8 +452,7 @@ uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size)
* do cache flushes. don't think any
* exist, so we ignore them.
*/
- if (!is_mx6dqp())
- writel(1, MX6DQ_PU_IROM_MMU_EN_VAR);
+ writel(1, MX6DQ_PU_IROM_MMU_EN_VAR);
} else if (is_cpu_type(MXC_CPU_MX6DL) ||
is_cpu_type(MXC_CPU_MX6SOLO)) {
writel(1, MX6DLS_PU_IROM_MMU_EN_VAR);
diff --git a/arch/arm/imx-common/sata.c b/arch/arm/imx-common/sata.c
index d174a46..76aad0e 100644
--- a/arch/arm/imx-common/sata.c
+++ b/arch/arm/imx-common/sata.c
@@ -15,7 +15,8 @@ int setup_sata(void)
struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
int ret;
- if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
+ if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D) &&
+ !is_cpu_type(MXC_CPU_MX6QP) && !is_cpu_type(MXC_CPU_MX6DP))
return 1;
ret = enable_sata_clock();
diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c
index e9fad86..f52c6b5 100644
--- a/arch/arm/imx-common/timer.c
+++ b/arch/arm/imx-common/timer.c
@@ -43,7 +43,8 @@ DECLARE_GLOBAL_DATA_PTR;
static inline int gpt_has_clk_source_osc(void)
{
#if defined(CONFIG_MX6)
- if (((is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) &&
+ if (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP) ||
+ ((is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) &&
(soc_rev() > CHIP_REV_1_0)) || is_cpu_type(MXC_CPU_MX6DL) ||
is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX) ||
is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6ULL))