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| author | Tom Rini <trini@konsulko.com> | 2016-06-02 21:42:23 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-06-02 21:42:23 -0400 |
| commit | edb697cfcc2dda02c5b2a34b3157b8fa8fc01264 (patch) | |
| tree | 347dadd1492b3dd4935532a11fe9e2d77b114266 /arch/arm/dts | |
| parent | e2924e5904ae413e0b4a2a0d407267e7bbc2c7c4 (diff) | |
| parent | d31e9c575f24f4b7f5f382ccae70d7a86bbc379d (diff) | |
| download | u-boot-imx-edb697cfcc2dda02c5b2a34b3157b8fa8fc01264.zip u-boot-imx-edb697cfcc2dda02c5b2a34b3157b8fa8fc01264.tar.gz u-boot-imx-edb697cfcc2dda02c5b2a34b3157b8fa8fc01264.tar.bz2 | |
Merge branch 'master' of git://git.denx.de/u-boot-socfpga
Diffstat (limited to 'arch/arm/dts')
| -rw-r--r-- | arch/arm/dts/Makefile | 3 | ||||
| -rw-r--r-- | arch/arm/dts/socfpga_cyclone5_vining_fpga.dts | 113 |
2 files changed, 115 insertions, 1 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 92c7545..e76f56b 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -107,7 +107,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_cyclone5_de0_nano_soc.dtb \ socfpga_cyclone5_sockit.dtb \ socfpga_cyclone5_socrates.dtb \ - socfpga_cyclone5_sr1500.dtb + socfpga_cyclone5_sr1500.dtb \ + socfpga_cyclone5_vining_fpga.dtb dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb dtb-$(CONFIG_TARGET_BEAGLE_X15) += am57xx-beagle-x15.dtb diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts new file mode 100644 index 0000000..f168e4f --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts @@ -0,0 +1,113 @@ +/* + * Copyright (C) 2015 Marek Vasut <marex@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "samtec VIN|ING FPGA"; + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + aliases { + ethernet0 = &gmac1; + udc0 = &usb0; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + + soc { + u-boot,dm-pre-reloc; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txen-skew-ps = <0>; + txc-skew-ps = <2600>; + rxdv-skew-ps = <0>; + rxc-skew-ps = <2000>; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rtc: rtc@68 { + compatible = "stm,m41t82"; + reg = <0x68>; + }; +}; + +&qspi { + status = "okay"; + u-boot,dm-pre-reloc; + + flash0: n25q128@0 { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q128", "spi-flash"; + reg = <0>; /* chip select */ + spi-max-frequency = <50000000>; + m25p,fast-read; + page-size = <256>; + block-size = <16>; /* 2^16, 64KB */ + read-delay = <4>; /* delay value in read data capture register */ + tshsl-ns = <50>; + tsd2d-ns = <50>; + tchsh-ns = <4>; + tslch-ns = <4>; + }; + + flash1: n25q00@1 { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q00", "spi-flash"; + reg = <1>; /* chip select */ + spi-max-frequency = <50000000>; + m25p,fast-read; + page-size = <256>; + block-size = <16>; /* 2^16, 64KB */ + read-delay = <4>; /* delay value in read data capture register */ + tshsl-ns = <50>; + tsd2d-ns = <50>; + tchsh-ns = <4>; + tslch-ns = <4>; + }; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; |