summaryrefslogtreecommitdiff
path: root/arch/arm/dts
diff options
context:
space:
mode:
authorBin Meng <bmeng.cn@gmail.com>2016-01-13 19:39:06 -0800
committerSimon Glass <sjg@chromium.org>2016-01-20 19:10:15 -0700
commit665ac00c9842bf45aacec2b9d8bd017ad201d7f9 (patch)
tree398f3392fd2b7476c60d21f5485c853014c23e2e /arch/arm/dts
parent8b67761437099c81c18f825f195c70a25fed0097 (diff)
downloadu-boot-imx-665ac00c9842bf45aacec2b9d8bd017ad201d7f9.zip
u-boot-imx-665ac00c9842bf45aacec2b9d8bd017ad201d7f9.tar.gz
u-boot-imx-665ac00c9842bf45aacec2b9d8bd017ad201d7f9.tar.bz2
arm: ls1021atwr: Enable driver model lpuart serial driver
Convert ls1021atwr_nor_lpuart to driver model support. As a start, enable lpuart serial port driver. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Alison Wang <alison.wang@nxp.com> Tested-by: Alison Wang <alison.wang@nxp.com> Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/arm/dts')
-rw-r--r--arch/arm/dts/Makefile2
-rw-r--r--arch/arm/dts/ls1021a-twr-lpuart.dts16
2 files changed, 17 insertions, 1 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 5a6f75a..7706b41 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -93,7 +93,7 @@ dtb-$(CONFIG_TARGET_BEAGLE_X15) += am57xx-beagle-x15.dtb
dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb
dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \
- ls1021a-twr-duart.dtb
+ ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb
dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
fsl-ls2080a-rdb.dtb
dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds.dtb \
diff --git a/arch/arm/dts/ls1021a-twr-lpuart.dts b/arch/arm/dts/ls1021a-twr-lpuart.dts
new file mode 100644
index 0000000..2941ec0
--- /dev/null
+++ b/arch/arm/dts/ls1021a-twr-lpuart.dts
@@ -0,0 +1,16 @@
+/*
+ * Freescale ls1021a TWR board device tree source
+ *
+ * Copyright 2013-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+#include "ls1021a-twr.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &lpuart0;
+ };
+};