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| author | Tom Warren <twarren@nvidia.com> | 2012-12-21 15:59:15 -0700 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2013-01-16 13:40:08 -0700 |
| commit | 083bbbbe771afce5e06793c6c831367b596cf03e (patch) | |
| tree | 650a4e0c6d9d22c07a64bb88b36e9cee50be91a1 /arch/arm/dts | |
| parent | 619bd99e5c176c736c3d1bb2e565ade38a103228 (diff) | |
| download | u-boot-imx-083bbbbe771afce5e06793c6c831367b596cf03e.zip u-boot-imx-083bbbbe771afce5e06793c6c831367b596cf03e.tar.gz u-boot-imx-083bbbbe771afce5e06793c6c831367b596cf03e.tar.bz2 | |
Tegra30: fdt: Update DT files with I2C info for T30/Cardhu
Note that T30 does not have a separate/different DVC (power I2C)
controller like T20 - all 5 I2C controllers are identical, but
DVC_I2C is still used to designate the controller intended for
power control (PWR_I2C in the schematics). On Cardhu, it's used
to access the PMU and EEPROM, as well as the audio codec, temp
sensor, and fuel gauge devices from the OS.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/dts')
| -rw-r--r-- | arch/arm/dts/tegra30.dtsi | 61 |
1 files changed, 61 insertions, 0 deletions
diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi index f568d44..664c397 100644 --- a/arch/arm/dts/tegra30.dtsi +++ b/arch/arm/dts/tegra30.dtsi @@ -2,4 +2,65 @@ / { compatible = "nvidia,tegra30"; + + tegra_car: clock@60006000 { + compatible = "nvidia,tegra30-car", "nvidia,tegra20-car"; + reg = <0x60006000 0x1000>; + #clock-cells = <1>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + osc: clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + }; + + i2c@7000c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000C000 0x100>; + /* PERIPH_ID_I2C1, CLK_M */ + clocks = <&tegra_car 12>; + }; + + i2c@7000c400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000C400 0x100>; + /* PERIPH_ID_I2C2, CLK_M */ + clocks = <&tegra_car 54>; + }; + + i2c@7000c500 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000C500 0x100>; + /* PERIPH_ID_I2C3, CLK_M */ + clocks = <&tegra_car 67>; + }; + + i2c@7000c700 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000C700 0x100>; + /* PERIPH_ID_I2C4, CLK_M */ + clocks = <&tegra_car 103>; + }; + + i2c@7000d000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000D000 0x100>; + /* PERIPH_ID_I2C_DVC, CLK_M */ + clocks = <&tegra_car 47>; + }; }; |