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author | Ye Li <ye.li@nxp.com> | 2017-03-06 14:43:13 +0800 |
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committer | Ye Li <ye.li@nxp.com> | 2017-04-05 14:05:05 +0800 |
commit | d5f904fc3c48871e084fdcea9de38aa1c3579122 (patch) | |
tree | e7a2583e68beaaff3eb336f3796212bbeecaf07f /arch/arm/dts/imx6q-sabreauto.dts | |
parent | 24066e390f71de726d972c2cf4a2d9b9718f7d3d (diff) | |
download | u-boot-imx-d5f904fc3c48871e084fdcea9de38aa1c3579122.zip u-boot-imx-d5f904fc3c48871e084fdcea9de38aa1c3579122.tar.gz u-boot-imx-d5f904fc3c48871e084fdcea9de38aa1c3579122.tar.bz2 |
MLK-14326-3 mx6qsabreauto: Enable OF_CONTROL and DM driver
Enable OF_CONTROL and DM driver on mx6qsabreauto.
1. Add the imx6qsabreauto relevant DTS file for using DTB.
2. Modify PMIC initialization codes to use DM PMIC driver.
3. Modify to use PCA953X DM driver
4. Remove NAND from default, since the default imx6q-sabreauto.dts disabled
the nand. The pins are conflicted with UART3, while UART3 is enabled.
5. For NAND build configuration, remove the USB, since the imx6q-sabreauto-gpmi-weim.dts
will have pin conflicts on steer logic.
6. GPIO requests added.
Signed-off-by: Ye Li <ye.li@nxp.com>
Diffstat (limited to 'arch/arm/dts/imx6q-sabreauto.dts')
-rw-r--r-- | arch/arm/dts/imx6q-sabreauto.dts | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/arch/arm/dts/imx6q-sabreauto.dts b/arch/arm/dts/imx6q-sabreauto.dts new file mode 100644 index 0000000..a321a20 --- /dev/null +++ b/arch/arm/dts/imx6q-sabreauto.dts @@ -0,0 +1,45 @@ +/* + * Copyright 2012-2015 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-sabreauto.dtsi" + +/ { + model = "Freescale i.MX6 Quad SABRE Automotive Board"; + compatible = "fsl,imx6q-sabreauto", "fsl,imx6q"; +}; + +&ldb { + lvds-channel@0 { + crtc = "ipu2-di0"; + }; + lvds-channel@1 { + crtc = "ipu2-di1"; + }; +}; +&mxcfb1 { + status = "okay"; +}; +&mxcfb2 { + status = "okay"; +}; +&mxcfb3 { + status = "okay"; +}; +&mxcfb4 { + status = "okay"; +}; +&sata { + status = "okay"; +}; |