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| author | Xu Ziyuan <xzy.xu@rock-chips.com> | 2016-09-05 09:39:58 +0800 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2016-10-01 18:35:01 -0600 |
| commit | 2179a07c0c7d1a87ccf13b3f3124c107de7dab91 (patch) | |
| tree | 4d28a3c57113654fdb1e705e9f067eafd57c2fb0 /arch/arm/dts/hi6220.dtsi | |
| parent | 45b047e557bdcf68dc08e61cf207dd35b9ba8bbc (diff) | |
| download | u-boot-imx-2179a07c0c7d1a87ccf13b3f3124c107de7dab91.zip u-boot-imx-2179a07c0c7d1a87ccf13b3f3124c107de7dab91.tar.gz u-boot-imx-2179a07c0c7d1a87ccf13b3f3124c107de7dab91.tar.bz2 | |
rockchip: rk3288: sdram: fix DDR address range
The all current Rockchip SoCs supporting 4GB of ram have problems
accessing the memory region 0xfe000000~0xff000000. Actually, some IP
controller can't address to, so let's limit the available range.
This patch fixes a bug which found in miniarm-rk3288-4GB board. The
U-Boot was relocated to 0xfef72000, and .bss variants was also
relocated, such as do_fat_read_at_block. Once eMMC controller transfer
data to do_fat_read_at_block via DMA, DMAC can't access more than
0xfe000000. So that DMAC didn't work sane.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/arm/dts/hi6220.dtsi')
0 files changed, 0 insertions, 0 deletions