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| author | Akshay Saraswat <akshay.s@samsung.com> | 2015-02-20 13:27:17 +0530 |
|---|---|---|
| committer | Minkyu Kang <mk7.kang@samsung.com> | 2015-02-28 18:03:46 +0900 |
| commit | 7e514eef02d2508a19be13d3efdf747c4e7ef5c5 (patch) | |
| tree | aff4796e19e86f23d01e1392961984740cb1da6d /arch/arm/dts/exynos5422-odroidxu3.dts | |
| parent | f0f76b0a4c7181b2cbde39ec04eac8973cd4ad1f (diff) | |
| download | u-boot-imx-7e514eef02d2508a19be13d3efdf747c4e7ef5c5.zip u-boot-imx-7e514eef02d2508a19be13d3efdf747c4e7ef5c5.tar.gz u-boot-imx-7e514eef02d2508a19be13d3efdf747c4e7ef5c5.tar.bz2 | |
Exynos542x: add L2 control register configuration
This patch does 3 things:
1. Enables ECC by setting 21st bit of L2CTLR.
2. Restore data and tag RAM latencies to 3 cycles because iROM sets
0x3000400 L2CTLR value during switching.
3. Disable clean/evict push to external by setting 3rd bit of L2ACTLR.
We need to restore this here due to switching.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'arch/arm/dts/exynos5422-odroidxu3.dts')
0 files changed, 0 insertions, 0 deletions