diff options
| author | Chandan Nath <chandan.nath@ti.com> | 2012-01-09 20:38:56 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-01-16 08:40:11 +0100 |
| commit | fb072a3ead8cc9f4a5e236a4b424e4df16f5e5ef (patch) | |
| tree | 012405e9b81d9f9a17f0cefc19a4053f439d2ca5 /arch/arm/cpu | |
| parent | f16da7466fc46109ba8922069cef521eb068f9a2 (diff) | |
| download | u-boot-imx-fb072a3ead8cc9f4a5e236a4b424e4df16f5e5ef.zip u-boot-imx-fb072a3ead8cc9f4a5e236a4b424e4df16f5e5ef.tar.gz u-boot-imx-fb072a3ead8cc9f4a5e236a4b424e4df16f5e5ef.tar.bz2 | |
ARM:AM33XX: Fix ddr and timer register offset
This patch is added to update incorrect ddr and timer
register offset.
Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/am33xx/board.c | 8 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/am33xx/clock.c | 3 |
2 files changed, 7 insertions, 4 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index 2d6d359..78db3a5 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -26,7 +26,7 @@ DECLARE_GLOBAL_DATA_PTR; struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; -struct timer_reg *timerreg = (struct timer_reg *)DM_TIMER2_BASE; +struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE; /* * early system init of muxing and clocks. @@ -55,12 +55,12 @@ void s_init(u32 in_ddr) void init_timer(void) { /* Reset the Timer */ - writel(0x2, (&timerreg->tsicrreg)); + writel(0x2, (&timer_base->tscir)); /* Wait until the reset is done */ - while (readl(&timerreg->tiocpcfgreg) & 1) + while (readl(&timer_base->tiocp_cfg) & 1) ; /* Start the Timer */ - writel(0x1, (&timerreg->tclrreg)); + writel(0x1, (&timer_base->tclr)); } diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c index 4ca6c45..7070e7d 100644 --- a/arch/arm/cpu/armv7/am33xx/clock.c +++ b/arch/arm/cpu/armv7/am33xx/clock.c @@ -101,6 +101,9 @@ static void enable_per_clocks(void) while (readl(&cmper->timer2clkctrl) != PRCM_MOD_EN) ; + /* Select the Master osc 24 MHZ as Timer2 clock source */ + writel(0x1, &cmdpll->clktimer2clk); + /* UART0 */ writel(PRCM_MOD_EN, &cmwkup->wkup_uart0ctrl); while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN) |