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| author | Tom Warren <twarren.nvidia@gmail.com> | 2011-12-06 13:00:19 +0000 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2011-12-21 20:36:22 +0100 |
| commit | e2132c29d8f445185bd87a7aeb297a285e0d9bfe (patch) | |
| tree | 719a37080fd46fee5ecb780a25d490616736c77d /arch/arm/cpu | |
| parent | 7aecfdd0f89ed866d85a67b830c5911964d6e095 (diff) | |
| download | u-boot-imx-e2132c29d8f445185bd87a7aeb297a285e0d9bfe.zip u-boot-imx-e2132c29d8f445185bd87a7aeb297a285e0d9bfe.tar.gz u-boot-imx-e2132c29d8f445185bd87a7aeb297a285e0d9bfe.tar.bz2 | |
arm: Tegra: fix undefined instruction hang immediately after reset
commit 0d479b53 (Aneesh V) added code for OMAP4 that doesn't
execute on Tegra, due to the AVP (ARM7TDI) not having a CP15.
Result was an undefined instruction hang just after reset.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Acked-by: Aneesh V <aneesh@ti.com>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/start.S | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 6a77c71..ef08a55 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -132,6 +132,7 @@ reset: orr r0, r0, #0xd3 msr cpsr,r0 +#if !defined(CONFIG_TEGRA2) /* * Setup vector: * (OMAP4 spl TEXT_BASE is not 32 byte aligned. @@ -147,6 +148,7 @@ reset: ldr r0, =_start mcr p15, 0, r0, c12, c0, 0 @Set VBAR #endif +#endif /* !Tegra2 */ /* the mask ROM code should have PLL and others stable */ #ifndef CONFIG_SKIP_LOWLEVEL_INIT |