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| author | Vladimir Zapolskiy <vz@mleia.com> | 2015-07-18 03:07:52 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-08-12 20:47:33 -0400 |
| commit | dcfd37e5ef17a3beec212fc4088f14f3fdcba5d1 (patch) | |
| tree | a3364f0f66a09564f1aeaafea0a5262fca7675ff /arch/arm/cpu | |
| parent | 8d1809a966996fdbcddb441c0ff8080d78a89c59 (diff) | |
| download | u-boot-imx-dcfd37e5ef17a3beec212fc4088f14f3fdcba5d1.zip u-boot-imx-dcfd37e5ef17a3beec212fc4088f14f3fdcba5d1.tar.gz u-boot-imx-dcfd37e5ef17a3beec212fc4088f14f3fdcba5d1.tar.bz2 | |
nand: lpc32xx: add SLC NAND controller support
The change adds support of LPC32xx SLC NAND controller.
LPC32xx SoC has two different mutually exclusive NAND controllers to
communicate with single and multiple layer chips.
This simple driver allows to specify NAND chip timings and defines
custom read_buf()/write_buf() operations, because access to 8-bit data
register must be 32-bit aligned.
Support of hardware ECC calculation is not implemented (data
correction is always done by software), since it requires a working
DMA engine.
The driver can be included to an SPL image.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c index 5a453e3..b0287be 100644 --- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c +++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c @@ -54,6 +54,12 @@ void lpc32xx_mlc_nand_init(void) writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, &clk->flashclk_ctrl); } +void lpc32xx_slc_nand_init(void) +{ + /* Enable SLC NAND interface */ + writel(CLK_NAND_SLC | CLK_NAND_SLC_SELECT, &clk->flashclk_ctrl); +} + void lpc32xx_i2c_init(unsigned int devnum) { /* Enable I2C interface */ |