Add TI816X support

Signed-off-by: Antoine Tenart <atenart@adeneo-embedded.com>
[trini: Fix warnings about vtp things in emif4.c, adapt AM43XX]
Signed-off-by: Tom Rini <trini@ti.com>

4 files changed, 452 insertions, 95 deletions

diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile
index bd8e752..f6a297c 100644
--- a/arch/arm/cpu/armv7/am33xx/Makefile
+++ b/arch/arm/cpu/armv7/am33xx/Makefile
@@ -16,6 +16,7 @@ ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX),)
 COBJS	+= clock.o
 endif
 
+COBJS-$(CONFIG_TI816X)	+= clock_ti816x.o
 COBJS	+= sys_info.o
 COBJS	+= mem.o
 COBJS	+= ddr.o
diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
index 93c7f7b..ef14f47 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
@@ -100,103 +100,8 @@ struct ad_pll {
 
 #define OSC_SRC_CTRL			(PLL_SUBSYS_BASE + 0x2C0)
 
-/* PRCM */
 #define ENET_CLKCTRL_CMPL		0x30000
 
-#define CM_DEFAULT_BASE			(PRCM_BASE + 0x0500)
-
-struct cm_def {
-	unsigned int resv0[2];
-	unsigned int l3fastclkstctrl;
-	unsigned int resv1[1];
-	unsigned int pciclkstctrl;
-	unsigned int resv2[1];
-	unsigned int ducaticlkstctrl;
-	unsigned int resv3[1];
-	unsigned int emif0clkctrl;
-	unsigned int emif1clkctrl;
-	unsigned int dmmclkctrl;
-	unsigned int fwclkctrl;
-	unsigned int resv4[10];
-	unsigned int usbclkctrl;
-	unsigned int resv5[1];
-	unsigned int sataclkctrl;
-	unsigned int resv6[4];
-	unsigned int ducaticlkctrl;
-	unsigned int pciclkctrl;
-};
-
-#define CM_ALWON_BASE			(PRCM_BASE + 0x1400)
-
-struct cm_alwon {
-	unsigned int l3slowclkstctrl;
-	unsigned int ethclkstctrl;
-	unsigned int l3medclkstctrl;
-	unsigned int mmu_clkstctrl;
-	unsigned int mmucfg_clkstctrl;
-	unsigned int ocmc0clkstctrl;
-	unsigned int vcpclkstctrl;
-	unsigned int mpuclkstctrl;
-	unsigned int sysclk4clkstctrl;
-	unsigned int sysclk5clkstctrl;
-	unsigned int sysclk6clkstctrl;
-	unsigned int rtcclkstctrl;
-	unsigned int l3fastclkstctrl;
-	unsigned int resv0[67];
-	unsigned int mcasp0clkctrl;
-	unsigned int mcasp1clkctrl;
-	unsigned int mcasp2clkctrl;
-	unsigned int mcbspclkctrl;
-	unsigned int uart0clkctrl;
-	unsigned int uart1clkctrl;
-	unsigned int uart2clkctrl;
-	unsigned int gpio0clkctrl;
-	unsigned int gpio1clkctrl;
-	unsigned int i2c0clkctrl;
-	unsigned int i2c1clkctrl;
-	unsigned int mcasp345clkctrl;
-	unsigned int atlclkctrl;
-	unsigned int mlbclkctrl;
-	unsigned int pataclkctrl;
-	unsigned int resv1[1];
-	unsigned int uart3clkctrl;
-	unsigned int uart4clkctrl;
-	unsigned int uart5clkctrl;
-	unsigned int wdtimerclkctrl;
-	unsigned int spiclkctrl;
-	unsigned int mailboxclkctrl;
-	unsigned int spinboxclkctrl;
-	unsigned int mmudataclkctrl;
-	unsigned int resv2[2];
-	unsigned int mmucfgclkctrl;
-	unsigned int resv3[2];
-	unsigned int ocmc0clkctrl;
-	unsigned int vcpclkctrl;
-	unsigned int resv4[2];
-	unsigned int controlclkctrl;
-	unsigned int resv5[2];
-	unsigned int gpmcclkctrl;
-	unsigned int ethernet0clkctrl;
-	unsigned int ethernet1clkctrl;
-	unsigned int mpuclkctrl;
-	unsigned int debugssclkctrl;
-	unsigned int l3clkctrl;
-	unsigned int l4hsclkctrl;
-	unsigned int l4lsclkctrl;
-	unsigned int rtcclkctrl;
-	unsigned int tpccclkctrl;
-	unsigned int tptc0clkctrl;
-	unsigned int tptc1clkctrl;
-	unsigned int tptc2clkctrl;
-	unsigned int tptc3clkctrl;
-	unsigned int resv7[4];
-	unsigned int dcan01clkctrl;
-	unsigned int mmchs0clkctrl;
-	unsigned int mmchs1clkctrl;
-	unsigned int mmchs2clkctrl;
-	unsigned int custefuseclkctrl;
-};
-
 #define SATA_PLL_BASE			(CTRL_BASE + 0x0720)
 
 struct sata_pll {
diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti816x.c b/arch/arm/cpu/armv7/am33xx/clock_ti816x.c
new file mode 100644
index 0000000..ace4a5a
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/clock_ti816x.c
@@ -0,0 +1,445 @@
+/*
+ * clock_ti816x.c
+ *
+ * Clocks for TI816X based boards
+ *
+ * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
+ * Antoine Tenart, <atenart@adeneo-embedded.com>
+ *
+ * Based on TI-PSP-04.00.02.14 :
+ *
+ * Copyright (C) 2009, Texas Instruments, Incorporated
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+#include <asm/emif.h>
+
+#define CM_PLL_BASE		(CTRL_BASE + 0x0400)
+
+/* Main PLL */
+#define MAIN_N			64
+#define MAIN_P			0x1
+#define MAIN_INTFREQ1		0x8
+#define MAIN_FRACFREQ1		0x800000
+#define MAIN_MDIV1		0x2
+#define MAIN_INTFREQ2		0xE
+#define MAIN_FRACFREQ2		0x0
+#define MAIN_MDIV2		0x1
+#define MAIN_INTFREQ3		0x8
+#define MAIN_FRACFREQ3		0xAAAAB0
+#define MAIN_MDIV3		0x3
+#define MAIN_INTFREQ4		0x9
+#define MAIN_FRACFREQ4		0x55554F
+#define MAIN_MDIV4		0x3
+#define MAIN_INTFREQ5		0x9
+#define MAIN_FRACFREQ5		0x374BC6
+#define MAIN_MDIV5		0xC
+#define MAIN_MDIV6		0x48
+#define MAIN_MDIV7		0x4
+
+/* DDR PLL */
+#if defined(CONFIG_TI816X_DDR_PLL_400) /* 400 MHz */
+#define DDR_N			59
+#define DDR_P			0x1
+#define DDR_MDIV1		0x4
+#define DDR_INTFREQ2		0x8
+#define DDR_FRACFREQ2		0xD99999
+#define DDR_MDIV2		0x1E
+#define DDR_INTFREQ3		0x8
+#define DDR_FRACFREQ3		0x0
+#define DDR_MDIV3		0x4
+#define DDR_INTFREQ4		0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ4		0x0
+#define DDR_MDIV4		0x4
+#define DDR_INTFREQ5		0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ5		0x0
+#define DDR_MDIV5		0x4
+#elif defined(CONFIG_TI816X_DDR_PLL_531) /* 531 MHz */
+#define DDR_N			59
+#define DDR_P			0x1
+#define DDR_MDIV1		0x3
+#define DDR_INTFREQ2		0x8
+#define DDR_FRACFREQ2		0xD99999
+#define DDR_MDIV2		0x1E
+#define DDR_INTFREQ3		0x8
+#define DDR_FRACFREQ3		0x0
+#define DDR_MDIV3		0x4
+#define DDR_INTFREQ4		0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ4		0x0
+#define DDR_MDIV4		0x4
+#define DDR_INTFREQ5		0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ5		0x0
+#define DDR_MDIV5		0x4
+#elif defined(CONFIG_TI816X_DDR_PLL_675) /* 675 MHz */
+#define DDR_N			50
+#define DDR_P			0x1
+#define DDR_MDIV1		0x2
+#define DDR_INTFREQ2		0x9
+#define DDR_FRACFREQ2		0x0
+#define DDR_MDIV2		0x19
+#define DDR_INTFREQ3		0x13
+#define DDR_FRACFREQ3		0x800000
+#define DDR_MDIV3		0x2
+#define DDR_INTFREQ4		0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ4		0x0
+#define DDR_MDIV4		0x4
+#define DDR_INTFREQ5		0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ5		0x0
+#define DDR_MDIV5		0x4
+#elif defined(CONFIG_TI816X_DDR_PLL_796) /* 796 MHz */
+#define DDR_N			59
+#define DDR_P			0x1
+#define DDR_MDIV1		0x2
+#define DDR_INTFREQ2		0x8
+#define DDR_FRACFREQ2		0xD99999
+#define DDR_MDIV2		0x1E
+#define DDR_INTFREQ3		0x8
+#define DDR_FRACFREQ3		0x0
+#define DDR_MDIV3		0x4
+#define DDR_INTFREQ4		0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ4		0x0
+#define DDR_MDIV4		0x4
+#define DDR_INTFREQ5		0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ5		0x0
+#define DDR_MDIV5		0x4
+#endif
+
+#define CONTROL_STATUS			(CTRL_BASE + 0x40)
+#define DDR_RCD				(CTRL_BASE + 0x070C)
+#define CM_TIMER1_CLKSEL		(PRCM_BASE + 0x390)
+#define DMM_PAT_BASE_ADDR		(DMM_BASE + 0x420)
+#define CM_ALWON_CUST_EFUSE_CLKCTRL	(PRCM_BASE + 0x1628)
+
+#define INTCPS_SYSCONFIG	0x48200010
+#define CM_SYSCLK10_CLKSEL	0x48180324
+
+struct cm_pll {
+	unsigned int mainpll_ctrl;	/* offset 0x400 */
+	unsigned int mainpll_pwd;
+	unsigned int mainpll_freq1;
+	unsigned int mainpll_div1;
+	unsigned int mainpll_freq2;
+	unsigned int mainpll_div2;
+	unsigned int mainpll_freq3;
+	unsigned int mainpll_div3;
+	unsigned int mainpll_freq4;
+	unsigned int mainpll_div4;
+	unsigned int mainpll_freq5;
+	unsigned int mainpll_div5;
+	unsigned int resv0[1];
+	unsigned int mainpll_div6;
+	unsigned int resv1[1];
+	unsigned int mainpll_div7;
+	unsigned int ddrpll_ctrl;	/* offset 0x440 */
+	unsigned int ddrpll_pwd;
+	unsigned int resv2[1];
+	unsigned int ddrpll_div1;
+	unsigned int ddrpll_freq2;
+	unsigned int ddrpll_div2;
+	unsigned int ddrpll_freq3;
+	unsigned int ddrpll_div3;
+	unsigned int ddrpll_freq4;
+	unsigned int ddrpll_div4;
+	unsigned int ddrpll_freq5;
+	unsigned int ddrpll_div5;
+	unsigned int videopll_ctrl;	/* offset 0x470 */
+	unsigned int videopll_pwd;
+	unsigned int videopll_freq1;
+	unsigned int videopll_div1;
+	unsigned int videopll_freq2;
+	unsigned int videopll_div2;
+	unsigned int videopll_freq3;
+	unsigned int videopll_div3;
+	unsigned int resv3[4];
+	unsigned int audiopll_ctrl;	/* offset 0x4A0 */
+	unsigned int audiopll_pwd;
+	unsigned int resv4[2];
+	unsigned int audiopll_freq2;
+	unsigned int audiopll_div2;
+	unsigned int audiopll_freq3;
+	unsigned int audiopll_div3;
+	unsigned int audiopll_freq4;
+	unsigned int audiopll_div4;
+	unsigned int audiopll_freq5;
+	unsigned int audiopll_div5;
+};
+
+const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE;
+const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE;
+const struct cm_pll *cmpll = (struct cm_pll *)CM_PLL_BASE;
+const struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
+
+void enable_dmm_clocks(void)
+{
+	writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl);
+	writel(PRCM_MOD_EN, &cmdef->emif0clkctrl);
+	writel(PRCM_MOD_EN, &cmdef->emif1clkctrl);
+
+	/* Wait for clocks to be active */
+	while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300)
+		;
+	/* Wait for emif0 to be fully functional, including OCP */
+	while (((readl(&cmdef->emif0clkctrl) >> 17) & 0x3) != 0)
+		;
+	/* Wait for emif1 to be fully functional, including OCP */
+	while (((readl(&cmdef->emif1clkctrl) >> 17) & 0x3) != 0)
+		;
+
+	writel(PRCM_MOD_EN, &cmdef->dmmclkctrl);
+	/* Wait for dmm to be fully functional, including OCP */
+	while (((readl(&cmdef->dmmclkctrl) >> 17) & 0x3) != 0)
+		;
+
+	/* Enable Tiled Access */
+	writel(0x80000000, DMM_PAT_BASE_ADDR);
+}
+
+/* assume delay is aprox at least 1us */
+static void ddr_delay(int d)
+{
+	int i;
+
+	/*
+	 * read a control register.
+	 * this is a bit more delay and cannot be optimized by the compiler
+	 * assuming one read takes 200 cycles and A8 is runing 1 GHz
+	 * somewhat conservative setting
+	 */
+	for (i = 0; i < 50*d; i++)
+		readl(CONTROL_STATUS);
+}
+
+static void main_pll_init_ti816x(void)
+{
+	u32 main_pll_ctrl = 0;
+
+	/* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */
+	main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
+	main_pll_ctrl &= 0xFFFFFFFB;
+	main_pll_ctrl |= BIT(2);
+	writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
+
+	/* Enable PLL by setting BIT3 in its ctrl reg */
+	main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
+	main_pll_ctrl &= 0xFFFFFFF7;
+	main_pll_ctrl |= BIT(3);
+	writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
+
+	/* Write the values of N,P in the CTRL reg  */
+	main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
+	main_pll_ctrl &= 0xFF;
+	main_pll_ctrl |= (MAIN_N<<16 | MAIN_P<<8);
+	writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
+
+	/* Power up clock1-7 */
+	writel(0x0, &cmpll->mainpll_pwd);
+
+	/* Program the freq and divider values for clock1-7 */
+	writel((1<<31 | 1<<28 | (MAIN_INTFREQ1<<24) | MAIN_FRACFREQ1),
+		&cmpll->mainpll_freq1);
+	writel(((1<<8) | MAIN_MDIV1), &cmpll->mainpll_div1);
+
+	writel((1<<31 | 1<<28 | (MAIN_INTFREQ2<<24) | MAIN_FRACFREQ2),
+		&cmpll->mainpll_freq2);
+	writel(((1<<8) | MAIN_MDIV2), &cmpll->mainpll_div2);
+
+	writel((1<<31 | 1<<28 | (MAIN_INTFREQ3<<24) | MAIN_FRACFREQ3),
+		&cmpll->mainpll_freq3);
+	writel(((1<<8) | MAIN_MDIV3), &cmpll->mainpll_div3);
+
+	writel((1<<31 | 1<<28 | (MAIN_INTFREQ4<<24) | MAIN_FRACFREQ4),
+		&cmpll->mainpll_freq4);
+	writel(((1<<8) | MAIN_MDIV4), &cmpll->mainpll_div4);
+
+	writel((1<<31 | 1<<28 | (MAIN_INTFREQ5<<24) | MAIN_FRACFREQ5),
+		&cmpll->mainpll_freq5);
+	writel(((1<<8) | MAIN_MDIV5), &cmpll->mainpll_div5);
+
+	writel((1<<8 | MAIN_MDIV6), &cmpll->mainpll_div6);
+
+	writel((1<<8 | MAIN_MDIV7), &cmpll->mainpll_div7);
+
+	/* Wait for PLL to lock */
+	while ((readl(&cmpll->mainpll_ctrl) & BIT(7)) != BIT(7))
+		;
+
+	/* Put the PLL in normal mode, disable bypass */
+	main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
+	main_pll_ctrl &= 0xFFFFFFFB;
+	writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
+}
+
+static void ddr_pll_bypass_ti816x(void)
+{
+	u32 ddr_pll_ctrl = 0;
+
+	/* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */
+	ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl);
+	ddr_pll_ctrl &= 0xFFFFFFFB;
+	ddr_pll_ctrl |= BIT(2);
+	writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl);
+}
+
+static void ddr_pll_init_ti816x(void)
+{
+	u32 ddr_pll_ctrl = 0;
+	/* Enable PLL by setting BIT3 in its ctrl reg */
+	ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl);
+	ddr_pll_ctrl &= 0xFFFFFFF7;
+	ddr_pll_ctrl |= BIT(3);
+	writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl);
+
+	/* Write the values of N,P in the CTRL reg  */
+	ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl);
+	ddr_pll_ctrl &= 0xFF;
+	ddr_pll_ctrl |= (DDR_N<<16 | DDR_P<<8);
+	writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl);
+
+	ddr_delay(10);
+
+	/* Power up clock1-5 */
+	writel(0x0, &cmpll->ddrpll_pwd);
+
+	/* Program the freq and divider values for clock1-3 */
+	writel(((0<<8) | DDR_MDIV1), &cmpll->ddrpll_div1);
+	ddr_delay(1);
+	writel(((1<<8) | DDR_MDIV1), &cmpll->ddrpll_div1);
+	writel((1<<31 | 1<<28 | (DDR_INTFREQ2<<24) | DDR_FRACFREQ2),
+		&cmpll->ddrpll_freq2);
+	writel(((1<<8) | DDR_MDIV2), &cmpll->ddrpll_div2);
+	writel(((0<<8) | DDR_MDIV3), &cmpll->ddrpll_div3);
+	ddr_delay(1);
+	writel(((1<<8) | DDR_MDIV3), &cmpll->ddrpll_div3);
+	ddr_delay(1);
+	writel((0<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3),
+		&cmpll->ddrpll_freq3);
+	ddr_delay(1);
+	writel((1<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3),
+		&cmpll->ddrpll_freq3);
+
+	ddr_delay(5);
+
+	/* Wait for PLL to lock */
+	while ((readl(&cmpll->ddrpll_ctrl) & BIT(7)) != BIT(7))
+		;
+
+	/* Power up RCD */
+	writel(BIT(0), DDR_RCD);
+}
+
+static void peripheral_enable(void)
+{
+	/* Wake-up the l3_slow clock */
+	writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl);
+
+	/*
+	 * Note on Timers:
+	 * There are 8 timers(0-7) out of which timer 0 is a secure timer.
+	 * Timer 0 mux should not be changed
+	 *
+	 * To access the timer registers we need the to be
+	 * enabled which is what we do in the first step
+	 */
+
+	/* Enable timer1 */
+	writel(PRCM_MOD_EN, &cmalwon->timer1clkctrl);
+	/* Select timer1 clock to be CLKIN (27MHz) */
+	writel(BIT(1), CM_TIMER1_CLKSEL);
+
+	/* Wait for timer1 to be ON-ACTIVE */
+	while (((readl(&cmalwon->l3slowclkstctrl)
+					& (0x80000<<1))>>20) != 1)
+		;
+	/* Wait for timer1 to be enabled */
+	while (((readl(&cmalwon->timer1clkctrl) & 0x30000)>>16) != 0)
+		;
+	/* Active posted mode */
+	writel(PRCM_MOD_EN, (DM_TIMER1_BASE + 0x54));
+	while (readl(DM_TIMER1_BASE + 0x10) & BIT(0))
+		;
+	/* Start timer1  */
+	writel(BIT(0), (DM_TIMER1_BASE + 0x38));
+
+	/* eFuse */
+	writel(PRCM_MOD_EN, CM_ALWON_CUST_EFUSE_CLKCTRL);
+	while (readl(CM_ALWON_CUST_EFUSE_CLKCTRL) != PRCM_MOD_EN)
+		;
+
+	/* Enable gpio0 */
+	writel(PRCM_MOD_EN, &cmalwon->gpio0clkctrl);
+	while (readl(&cmalwon->gpio0clkctrl) != PRCM_MOD_EN)
+		;
+	writel((BIT(8)), &cmalwon->gpio0clkctrl);
+
+	/* Enable spi */
+	writel(PRCM_MOD_EN, &cmalwon->spiclkctrl);
+	while (readl(&cmalwon->spiclkctrl) != PRCM_MOD_EN)
+		;
+
+	/* Enable i2c0 */
+	writel(PRCM_MOD_EN, &cmalwon->i2c0clkctrl);
+	while (readl(&cmalwon->i2c0clkctrl) != PRCM_MOD_EN)
+		;
+
+	/* Enable ethernet0 */
+	writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl);
+	writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl);
+	writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl);
+
+	/* Enable hsmmc */
+	writel(PRCM_MOD_EN, &cmalwon->sdioclkctrl);
+	while (readl(&cmalwon->sdioclkctrl) != PRCM_MOD_EN)
+		;
+}
+
+void setup_clocks_for_console(void)
+{
+	/* Fix ROM code bug - from TI-PSP-04.00.02.14 */
+	writel(0x0, CM_SYSCLK10_CLKSEL);
+
+	ddr_pll_bypass_ti816x();
+
+	/* Enable uart0-2 */
+	writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl);
+	while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN)
+		;
+	writel(PRCM_MOD_EN, &cmalwon->uart1clkctrl);
+	while (readl(&cmalwon->uart1clkctrl) != PRCM_MOD_EN)
+		;
+	writel(PRCM_MOD_EN, &cmalwon->uart2clkctrl);
+	while (readl(&cmalwon->uart2clkctrl) != PRCM_MOD_EN)
+		;
+	while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100)
+		;
+}
+
+void prcm_init(void)
+{
+	/* Enable the control */
+	writel(PRCM_MOD_EN, &cmalwon->controlclkctrl);
+
+	main_pll_init_ti816x();
+	ddr_pll_init_ti816x();
+
+	/*
+	 * With clk freqs setup to desired values,
+	 * enable the required peripherals
+	 */
+	peripheral_enable();
+}
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
index 21cefd4..59ad25c 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -40,9 +40,11 @@ void dram_init_banksize(void)
 static struct dmm_lisa_map_regs *hw_lisa_map_regs =
 				(struct dmm_lisa_map_regs *)DMM_BASE;
 #endif
+#ifndef CONFIG_TI816X
 static struct vtp_reg *vtpreg[2] = {
 				(struct vtp_reg *)VTP0_CTRL_ADDR,
 				(struct vtp_reg *)VTP1_CTRL_ADDR};
+#endif
 #ifdef CONFIG_AM33XX
 static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
 #endif
@@ -64,6 +66,7 @@ void config_dmm(const struct dmm_lisa_map_regs *regs)
 }
 #endif
 
+#ifndef CONFIG_TI816X
 static void config_vtp(int nr)
 {
 	writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE,
@@ -78,6 +81,7 @@ static void config_vtp(int nr)
 			VTP_CTRL_READY)
 		;
 }
+#endif
 
 void __weak ddr_pll_config(unsigned int ddrpll_m)
 {
@@ -88,7 +92,9 @@ void config_ddr(unsigned int pll, unsigned int ioctrl,
 		const struct emif_regs *regs, int nr)
 {
 	ddr_pll_config(pll);
+#ifndef CONFIG_TI816X
 	config_vtp(nr);
+#endif
 	config_cmd_ctrl(ctrl, nr);
 
 	config_ddr_data(data, nr);