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authorMarek Vasut <marex@denx.de>2012-08-28 15:15:53 +0000
committerStefano Babic <sbabic@denx.de>2012-09-04 11:57:57 +0200
commitd82f05fcad3873dd6f5f06e042a28bacf2f0f950 (patch)
tree817bc53bdb50a098da5ca78907098224b9755675 /arch/arm/cpu
parent8aa09026588abb7222bc09c944db36312c263aad (diff)
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MX28: Fixup the ad-hoc use of DIGCTL_MICROSECONDS
Use proper struct-based access for this register in the SPL code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r--arch/arm/cpu/arm926ejs/mxs/spl_boot.c8
1 files changed, 5 insertions, 3 deletions
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
index ddafddb..ad66c57 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
@@ -38,12 +38,14 @@
* takes a few seconds to roll. The boot doesn't take that long, so to keep the
* code simple, it doesn't take rolling into consideration.
*/
-#define HW_DIGCTRL_MICROSECONDS 0x8001c0c0
void early_delay(int delay)
{
- uint32_t st = readl(HW_DIGCTRL_MICROSECONDS);
+ struct mxs_digctl_regs *digctl_regs =
+ (struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
+
+ uint32_t st = readl(&digctl_regs->hw_digctl_microseconds);
st += delay;
- while (st > readl(HW_DIGCTRL_MICROSECONDS))
+ while (st > readl(&digctl_regs->hw_digctl_microseconds))
;
}