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authorSimon Glass <sjg@chromium.org>2011-09-21 12:40:05 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2011-10-27 21:56:29 +0200
commitc3cf49d247d6749bdb65d9538ecd2738195e6a21 (patch)
tree85df919c2faf4991e636d6c6599cdebcf2320a9f /arch/arm/cpu
parent4ed59e70e4e0309794d532120d8c357b308b0e23 (diff)
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tegra2: Rename PIN_ to PINGRP_
The pin groupings are better named PINGRP, since on Tegra2 they refer to multiple pins. Sorry about this, but better to get it right now when there is only a small amount of code affected. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r--arch/arm/cpu/armv7/tegra2/pinmux.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/cpu/armv7/tegra2/pinmux.c b/arch/arm/cpu/armv7/tegra2/pinmux.c
index 5594ab8..01a3d84 100644
--- a/arch/arm/cpu/armv7/tegra2/pinmux.c
+++ b/arch/arm/cpu/armv7/tegra2/pinmux.c
@@ -27,7 +27,7 @@
#include <common.h>
-void pinmux_set_tristate(enum pmux_pin pin, int enable)
+void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
{
struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
u32 *tri = &pmt->pmt_tri[TRISTATE_REG(pin)];
@@ -41,12 +41,12 @@ void pinmux_set_tristate(enum pmux_pin pin, int enable)
writel(reg, tri);
}
-void pinmux_tristate_enable(enum pmux_pin pin)
+void pinmux_tristate_enable(enum pmux_pingrp pin)
{
pinmux_set_tristate(pin, 1);
}
-void pinmux_tristate_disable(enum pmux_pin pin)
+void pinmux_tristate_disable(enum pmux_pingrp pin)
{
pinmux_set_tristate(pin, 0);
}